View UPD61051GD-LML_1666105.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd61051, 61052 mpeg2 audio/video encoder document no. s15082ej4v0ds00 (4th edition) date published november 2003 ns cp (k) printed in japan data sheet the pd61051 and pd61052 are lsis of mpeg audio and vi deo encoding, decoding and transcoding. the pd61051 has mpeg2 video encoder, mpeg audio encoding d sp, 32-bit risc cpu, video input/output unit which contains a processing filter and a time base corrector (tbc), and mpeg system layer which contains the multiplexer and de-multiplexer. it combines wit h 64 m or 128 mbit sdram and it uses. the pd61052 has a dolby? digital consumer encoder in addition to the pd61051. the pd61051, 61052 are the optimal choice fo r consumer digital video recording replay equipment to process a mpeg. features ? video encode - stream standard: mpeg2 video mp@m l, sp@ml standard, mpeg1 standard - picture size: horizontal: 720, 704, 544, 480, 352 dots/line vertical: 480, 240, 576, 288 line/frame - single pass variable bit rate (vbr), constant bit rate (cbr) encoding - transcoding: bit rate conversion, vbr ? cbr - video input/output format: 8-bit y/cb/cr 4:2:2 (itu-r bt.656) pre analysis: film detect, scene changing detect, and motion estimation assist tbc, vbi data slicer ? audio encoding - bit length: 16 bits, 20 bits, 24 bits - sampling rate: 32 khz, 44.1 khz, 48 khz - mpeg1 audio layer 2 standard based - dolby digital consumer en coder standard based (only the pd61052) - elementary stream and pcm audio input/output ? mpeg system processing - multiplex: mpeg2-ps, mpeg 2-ts, dvd-video, and dvd-vr - de-multiplex: mpeg2-ps, mpeg2-ts - transcoding: mpeg2 format conversion (mpeg2-ts ? mpeg2-ps) - partial ts generation ? package: 208-pin fine pitch qfp ? power supply: 1200 mw (typ.) ? power supply voltage: 3.30.165 v, 2. 50.2 v (internal circuit power) "dolby" is a trademark of dolby laboratories. to use the pd61052, a license from dolby laboratori es licensing corporation is necessary. 2002 the mark shows major revised points.
data sheet s15082ej4v0ds 2 pd61051, 61052 application d-vhs, dvd video recorder, hdd video recorder ordering information part number package pd61051gd-lml 208-pin plastic qfp (fine pitch) (28 28) pd61051gd-lml-a note 208-pin plastic qfp (fine pitch) (28 28) pd61052gd-lml 208-pin plastic qfp (fine pitch) (28 28) pd61052gd-lml-a note 208-pin plastic qfp (fine pitch) (28 28) note lead-free product block diagram sdram interface unit mclke cmode2 ccs ovout7-ovout0/fa19-fa14 ovclk ivhsync ivvsync ivfld ivin7-ivin0 ivclk cre cwe/csdi ca5-ca0/fa5-fa0 cd7-cd0/fd7-fd0 cwait/foe cint cmode1/csdo osreq osvld/osrdy ossync osclk/osstb os7-os0/fa13-fa6 isreq isvld isclk/isstb is7-is2 reset iabd iabck ialrck oabd oabck oalrck amclk pwm mclk mcs mras mcas mwe mdqm pstop sclk (27 mhz) ma13-ma0 md31-md0 video input unit video output unit internal cpu system control unit pll audio dsp engine video encode/transcode unit host cpu interface unit stream interface unit gpo6/ovvsync gpo5/ovhsync gpio4-gpio0 cmode0/csclk is1/iserr is0 stclk
data sheet s15082ej4v0ds 3 pd61051, 61052 peripheral connection video input ntsc/pal decoder mpeg2 av encoder pd61051/61052 1394 av link 1394 phy adc dac sdram sdram ts decoder mpeg decoder stream interface pcm pcm bt.656 audio input 1394 in/out video output audio output host cpu ts av hdd
data sheet s15082ej4v0ds 4 pd61051, 61052 this lsi deals with two kinds of methods to connect a system controller. parallel bus interface 64m sdram ntsc/pal decoder ntsc/pal encoder audio adc audio adc/dac 27 mhz stc clock mpeg ts/ps user interface host cpu mpeg ts/ps bt.656 pcm bt.656 pcm pd61051/61052 serial bus interface 64m sdram ntsc/pal decoder ntsc/pal encoder audio adc audio adc/dac 27 mhz stc clock mpeg ts/ps user interface host cpu spi instruction rom mpeg ts/ps bt.656 pcm bt.656 pcm pd61051/61052
data sheet s15082ej4v0ds 5 pd61051, 61052 pin configuration (top view) ? 208-pin plastic qfp (fine pitch) (28 28) pd61051gd-lml pd61051gd-lml-a pd61052gd-lml pd61052gd-lml-a v dd2 amclk gnd oalrck oabck oabd ialrck iabck iabd gnd ivfld ivhsync v dd2 ivvsync gnd ivin0 ivin1 ivin2 ivin3 ivin4 ivin5 ivin6 ivin7 v dd2 ivclk gnd gnd sclk pstop pv dd2 pgnd pv dd2 pgnd stclk gnd v dd2 gnd gnd v dd3 pwm gnd is0 is1/iserr is2 is3 is4 is5 v dd2 is6 gnd is7 issync 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 isclk/isstb isvld isreq os0/fa6 os1/fa7 os2/fa8 os3/fa9 v dd2 os4/fa10 gnd os5/fa11 os6/fa12 os7/fa13 osclk/osstb ossync osvld/osrdy v dd3 osreq v dd2 md23 gnd gnd md22 md21 md20 md19 md18 md17 md16 v dd2 md24 gnd md25 v dd3 md26 gnd md27 md28 md29 md30 md31 v dd2 ma0 gnd ma1 v dd3 ma2 gnd ma3 ma10 ma12 ma13 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 ovout7 ovout6 ovout5/fa19 ovout4/fa18 ovout3/fa17 ovout2/fa16 ovout1/fa15 ovout0/fa14 gnd ovclk v dd2 gpo6/ovvsync gnd gpo5/ovhsync v dd3 gpio4 gpio3 gpio2 gpio1 gpio0 gnd ca5/fa5 v dd2 ca4/fa4 ca3/fa3 ca2/fa2 ca1/fa1 ca0/fa0 ndo ndi nmod gnd nrst v dd2 nclk gnd cd7/fd7 v dd3 cd6/fd6 cd5/fd5 cd4/fd4 cd3/fd3 cd2/fd2 gnd cd1/fd1 v dd2 cd0/fd0 cwait/foe cre ccs cmode2 cwe/csdi 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 cmode1/csdo cmode0/csclk gnd cint v dd2 reset gnd md15 v dd3 md14 md13 md12 md11 md10 gnd md9 v dd2 md8 md0 gnd md1 v dd3 md2 md3 md4 md5 gnd md6 v dd2 md7 mdqm mwe gnd mcas v dd3 mras mcs gnd mclk v dd2 mclke ma11 ma9 ma8 gnd ma7 v dd3 ma6 ma5 gnd ma4 v dd2
data sheet s15082ej4v0ds 6 pd61051, 61052 pin list amclk :audio main clock ma 0 to ma13 :memory address ca0/fa0 to ca5/fa5 :host cpu address/ mcas :memory column address strobe instruction rom addr ess mclk :m emory clock ccs :host cpu chip select mclke :memory clock enable cd0/fd0 to cd7/fd7 :host cpu data/ mcs :memory chip select instruction rom data md0 to md31 :memory data cint :host cpu interrupt md qm :memory dq mask enable cmode0/csclk :host cpu mode/ mras :memory row address strobe spi clock mwe :memory write enable cmode1/csdo :host cpu mode/ nclk :n-wire clock spi data output ndi :n-wire data input cmode2 :host cpu mode ndo :n-wire data output cre :host cpu read enable nmod :n-wire mode cwait/foe :host cpu wait/ nrst :n-wire reset instruction rom output enable oabck :output audio bit clock cwe/csdi :host cpu write enable/ oabd :output audio bit data spi data input oalrck :output audio lr clock gnd :ground os0/fa6 to os7/fa13 :output stream data/ gpio0 to gpio4 :general purpose io instruction rom address gpo5/ovhsync :general purpose output/ os clk/osstb :output stream data clock/ output video horizontal sync output stream data strobe gpo6/ovvsync :general purpose output/ osreq :output stream data request output video vertical sync ossync :output stream data sync iabck :input audio bit clock osvld/osrdy :output stream data valid/ iabd :input audio bit data output stream data ready ialrck :input audio lr clo ck ovclk :output video clock is0, is2 to is7 :input stream data ovout0/fa14 to :output video data/ is1/iserr :input stream data/ input stream error ovout5/fa19 instruction rom address isclk/isstb :input stream data clock/ ovout6,ovout7 :output video data input stream data strobe pgnd :pll ground isreq :input stream data request pstop :pll stop issync :input stream data sync pv dd2 :pll 2.5 v power supply isvld :input stream data valid pwm :pwm output ivclk :input video clock reset :reset ivfld :input video field i ndex sclk :system clock ivhsync :input video horizontal sy nc stclk :system time clock ivin0 to ivin7 :input video data v dd2 :2.5 v power supply ivvsync :input video vertical sync v dd3 :3.3 v power supply
data sheet s15082ej4v0ds 7 pd61051, 61052 contents 1. pin function ............................................................................................................... ................ 9 1.1 video input interface...................................................................................................... ....................... 9 1.2 video out put inte rface ..................................................................................................... ..................... 9 1.3 audio inpu t interf ace ...................................................................................................... ...................... 9 1.4 audio input/ou tput in terf ace ............................................................................................... ............... 10 1.5 stream i nput inte rface ..................................................................................................... ................... 10 1.6 stream out put interface .................................................................................................... ................. 11 1.7 sdram interf ace ............................................................................................................ ..................... 11 1.8 host cp u inte rface ......................................................................................................... ..................... 12 1.8.1 parallel bus interface................................................................................................... .............. 12 1.8.2 serial bu s interf ace..................................................................................................... ............... 12 1.9 clock, r eset ............................................................................................................... .......................... 13 1.10 n- wire.................................................................................................................... ............................... 13 1.11 gpio ...................................................................................................................... ............................... 14 1.12 powe r supply .............................................................................................................. ........................ 14 1.13 recommended connecti ons of unused pins ................................................................................... 1 5 2. feature overview........................................................................................................... ....... 16 2.1 vi deo ...................................................................................................................... .............................. 16 2.1.1 en codi ng ................................................................................................................. .................. 16 2.1.2 tran scodi ng.............................................................................................................. ................. 16 2.1.3 input/outpu t processing .................................................................................................. ........... 17 2.2 audio ...................................................................................................................... .............................. 19 2.2.1 en codi ng ................................................................................................................. .................. 19 2.2.2 transcoding (demux, mux) ................................................................................................. ... 19 2.2.3 input/outpu t processing .................................................................................................. ........... 19 2.3 mpeg syst em pro cessing ..................................................................................................... ............. 22 2.3.1 system time cl ock ........................................................................................................ ............. 22 2.3.2 mult iplex ................................................................................................................ .................... 23 2.3.3 de-mu ltiplex ............................................................................................................. ................. 23 2.3.4 tr anscode ................................................................................................................ ................. 24 2.4 stream interface ........................................................................................................... ....................... 25 2.4.1 parallel steam data inte rface ............................................................................................ ......... 25 2.4.2 serial stream data in terface............................................................................................. .......... 29 2.5 host cp u inte rface ......................................................................................................... ..................... 32 2.6 sdram interf ace ............................................................................................................ ..................... 33 2.7 memory conn ection diagram .................................................................................................. .......... 34 2.8 memory map ................................................................................................................. ....................... 36 3. system interface register .............................................................................................. 38 3.1 register mappin g (general mapping)......................................................................................... ....... 39 3.2 register functions......................................................................................................... ..................... 40 3.2.1 common regist er.......................................................................................................... ............. 40 3.2.2 data trans fer regi ster................................................................................................... .............. 40 3.2.3 internal cpu interrupt regist er.......................................................................................... ......... 47 3.2.4 interrupt mask regi ster .................................................................................................. ............ 47
data sheet s15082ej4v0ds 8 pd61051, 61052 3.2.5 download in terrupt r egister .............................................................................................. ......... 47 3.2.6 interrupt regi ster ....................................................................................................... ................. 48 3.2.7 reset regist er ........................................................................................................... ................. 48 3.2.8 rom access cycle regi ster................................................................................................ ........ 49 3.2.9 port se tup regi ster ...................................................................................................... ............... 49 4. system interface procedure.......................................................................................... 50 4.1 outline .................................................................................................................... .............................. 51 4.2 firmware download .......................................................................................................... .................. 52 4.2.1 host cpu to instructi on ram of inte rnal cp u ........................................................................... 52 4.2.2 external rom to instruct ion ram of inte rnal cp u..................................................................... 53 4.2.3 host cp u to s dram........................................................................................................ ......... 54 4.2.4 external rom to sdram .................................................................................................... ...... 55 4.3 sdram write during e xecuting ............................................................................................... .......... 56 4.4 sdram read during e xecuting ................................................................................................ ......... 57 4.5 sdram init ializa tion....................................................................................................... ..................... 58 4.6 operation mode setting by changing firmwa re .............................................................................. 59 4.7 transfer ending............................................................................................................ ....................... 60 4.8 transfer er ror handling .................................................................................................... .................. 61 4.8.1 transfer e rror handl ing 1 ................................................................................................ ........... 61 4.8.2 transfer e rror handl ing 2 ................................................................................................ ........... 62 4.8.3 transfer e rror handl ing 3 ................................................................................................ ........... 63 5. example for common register usage....................................................................... 64 5.1 register map exam ple ....................................................................................................... ................. 65 5.2 example of the common regist er which a firmw are defi nes ....................................................... 67 5.2.1 comcode: comm and code regi ster ........................................................................................ 66 5.2.2 ests: stat us regi ster .................................................................................................... ............ 66 6. electrical characteristics............................................................................................. 68 7. package drawing ............................................................................................................ .... 102 8. recommended soldering co nditions......................................................................... 103
data sheet s15082ej4v0ds 9 pd61051, 61052 1. pin function sharing pin is bold faced in name and explains the feature shown. 1.1 video input interface the video input is based on the itu-r bt.656 format. t he horizontal synchronization signal, and the vertical synchronization signal, the field index can be used with out using sav and eav to provid e at itu-r bt. 656, too. name io pin number function active polarity ivin7 to ivin0 i 23 to 16 video data ivclk i 25 video clock (27 mhz) ivhsync i 12 horizontal synchronization l ivvsync i 14 vertical synchronization l ivfld i 11 field index 1.2 video output interface the video output is based on the itu-r bt.656 format. it is able to output horizontal and vertical synchronization signals with sav/eav. these synchroniza tion signals are chosen output by t he firmware. these ports become gpo until the firmware initializes after hardware reset. at the time of the odd field, ovvsync falls in the 4th clock after falling of ovhsync. at the time of the even field, ovvsync falls in to the h/2+4th clo ck the ovhsync falling. name io pin number function active polarity ovout7, ovout6 o 208, 207 video data ovout5 to ovout0 / fa19 to fa14 o 206 to 201 video data ovclk o 199 video clock (27 mhz) gpo5/ ovhsync o 195 horizontal synchronization l gpo6/ ovvsync o 197 vertical synchronization l 1.3 audio input interface name io pin number function active polarity ialrck i 7 left/right clock iabck i 8 bit clock iabd i 9 bit data
data sheet s15082ej4v0ds 10 pd61051, 61052 1.4 audio input/output interface after hardware reset, it becomes input. oalrck, oabck and oabd connect with 3.3 v v dd through the 10 k ? pull up resistance. firmware cont rols input/output of those pins. name io pin number function active polarity oalrck io 4 left/right clock oabck io 5 bit clock oabd io 6 bit data amclk i 2 audio clock 1.5 stream input interface stream input corresponds to mpeg ts/ps stream. when slave mode (mpeg2-ts input with using valid signal), data input is possible to select 8 bits parallel data or seri al data mode. when serial data mode, data input to is0. active polarity of isreq is sele cted by the port setup register. active polarity of isclk/isstb, issy nc iserr and isvld are selected by firmware. these are unsettled after the turning on. name io pin number function active polarity isreq o 55 stream data request only parallel interface, this pin is active. after reset, default is active low. isclk/ isstb i 53 stream data strobe after reset, default is isclk. isclk /isstb i 53 stream data clock after reset, default is active high edge. issync i 52 stream data synchronization after reset, default is active high. isvld i 54 stream data valid after reset, default is active low. is1/ iserr i 43 stream error after reset, default is active high. is1 /iserr i 43 stream data input is7 to is2, is0 i 51,49, 47 to 44, 42 stream data input remark in this table, means of reset are hardware reset by the reset pin and all reset of the reset register.
data sheet s15082ej4v0ds 11 pd61051, 61052 1.6 stream output interface this interface outputs mpeg ts/ps st ream. when in master mode (mpeg2- ts output with using valid signal), data output is possible to select 8bits parallel data or se rial data mode. in serial mo de, data output from os0. active polarity of osvld is sele cted by the port setup register. active polarity of osclk/osstb and ossync are selected by firmware. these are unsettled after the turning on. name io pin number function active polarity osreq i 70 stream data request in slave mode l osclk/ osstb o 66 stream data strobe after reset, default is active high edge. osclk /osstb o 66 stream data clock after reset, default is osstb. ossync o 67 stream data synchronization after reset, default is active high. osvld /osrdy o 68 stream data valid after reset, default is osrdy. osvld/ osrdy o 68 stream data ready prepared after reset, default is active low. os7 to os0 / fa13 to fa6 o 65 to 63, 61, 59 to 56 stream data output remark in this table, means of reset are hardware reset by the reset pin and all reset of the reset register. 1.7 sdram interface name io pin number function active polarity ma13 to ma0 o 104, 103, 115, 102, 114, 113, 111, 109, 108, 106, 101, 99, 97, 95 address of row/column md31 to md0 io 93 to 89, 87, 85, 83, 72, 75 to 81, 149, 147 to 143, 141, 139, 127, 129, 131 to 134, 136, 138 data (built-in 50 k ? pull up resistor) mclk o 118 clock mcke o 116 clock enable h mcs o 120 chip selection l mras o 121 row address strobe l mcas o 123 column address strobe l mwe o 125 write enable l mdqm o 126 data input/output mask enable l
data sheet s15082ej4v0ds 12 pd61051, 61052 1.8 host cpu interface it chooses a parallel bus connection and a serial bus connection by the setting of cmode2. name io pin number function active polarity cmode2 i 158 host cpu interface select l: parallel, h: serial 1.8.1 parallel bus interface name io pin number function active polarity ca5 to ca0 / fa5 to fa0 i 187, 185 to 181 address cd7 to cd0 / fd7 to fd0 io 172, 170 to 166, 164, 162 data cwe /csdi i 157 write enable l cre i 160 read enable l ccs i 159 chip selection l cint o 153 interrupt h cwait /foe o 161 wait cmode0 /csclk i 155 setting of polarity of cwait l: low wait, h: high wait cmode1 /csdo i 156 setting of operation of cwait (built-in 50 k ? pull up resistor) l: wait operation.(after ready, pin continues ready) h: ready operation.(after ready, pin turns to wait) 1.8.2 serial bus interface when connecting a serial bus, it downloads instruct ion of internal cpu from instruction rom. (1) serial bus interface name io pin number function active polarity cmode0/ csclk i 155 spi serial interface clock fix csclk to high level during ccs is disable (high level). cwe/ csdi i 157 spi serial interface data input cmode1/ csdo o 156 spi serial interface data output (built-in 50 k ? pull up resistor) ccs i 159 chip selection l cint o 153 interrupt h
data sheet s15082ej4v0ds 13 pd61051, 61052 (2) instruction rom interface name io pin number function active polarity ca5 to ca0/ fa5 to fa0 o 187, 185 to 181 address os7 to os0/ fa13 to fa6 o 65 to 63, 61, 59 to 56 address ovout5 to ovout0/ fa19 to fa14 o 206 to 201 address cd7 to cd0/ fd7 to fd0 i 172, 170 to 166, 164, 162 data cwait/ foe o 161 output enable l 1.9 clock, reset name io pin number function active polarity sclk i 28 system clock stclk i 34 system time clock pstop i 29 internal pll operation control l: normal, h: internal pll stop h pwm o 40 pwm output reset i 151 reset l 1.10 n-wire ie port for firmware of internal cpu evaluation when not connecting an in-circuit emulat or, take countermeasures against noise by pulling up the ndi pin to avoid the pin becoming low level. name io pin number function active polarity nmod i 178 pin used when connecting ie pull up when connecting ie h nclk i 174 serial clock nrst i 176 n-wire reset l ndi i 179 data input ndo o 180 data output
data sheet s15082ej4v0ds 14 pd61051, 61052 1.11 gpio gpio becomes input after hardware reset by the reset pin and all reset by the reset register. gpio connect with 3.3 v v dd through the 10 k ? pull up resistance. name io pin number function active polarity gpio0 io 189 firmware use pin gpio1 io 190 firmware use pin gpio2 io 191 firmware use pin gpio3 io 192 firmware use pin gpio4 io 193 firmware use pin gpo5/ovhsync o 195 firmware use pin gpo6/ovvsync o 197 firmware use pin 1.12 power supply name io pin number function active polarity v dd3 - 39, 69, 86, 98, 110, 122, 135, 148, 171, 194 3.3 v power supply for interface v dd2 - 1, 13, 24, 36, 48, 60, 71, 82, 94, 105, 117, 128, 140, 152, 163, 175, 186, 198 2.5 v power supply for the internal circuit gnd - 3, 10, 15, 26, 27, 35, 37, 38, 41, 50, 62, 73, 74, 84, 88, 96, 100, 107, 112, 119, 124, 130, 137, 142, 150, 154, 165, 173, 177, 188, 196, 200 gnd pv dd2 - 30, 32 2.5 v power supply for pll pgnd - 31, 33 gnd for pll
data sheet s15082ej4v0ds 15 pd61051, 61052 1.13 recommended connections of unused pins connect unused pins as follows. name io connection ivin7 to ivin0 i gnd ivclk i gnd ivhsync i gnd ivvsync i gnd ivfld i gnd ovout7, ovout6 o open ovout5 to ovout0/fa19 to fa14 o open ovclk o open ialrck i gnd iabck i gnd iabd i gnd oalrck io pull up with 10 k ? resistor oabck io pull up with 10 k ? resistor oabd io pull up with 10 k ? resistor amclk i gnd isreq o open isclk/isstb i gnd issync i gnd isvld i gnd is7 to is0 i gnd osreq i gnd ossync o open ca5 to ca0/fa5 to fa0 io open cd7 to cd0/fd7 to fd0 io pull up with 10 k ? resistor cre i gnd cint o open cwait/foe o open pwm o open nmod i pull up with 4.7 k ? resistor nclk i pull up with 4.7 k ? resistor nrst i pull down with 50 k ? resistor ndi i pull up with 4.7 k ? resistor ndo o pull up with 4.7 k ? resistor gpio4 to gpio0 io pull up with 10 k ? resistor gpo5/ovhsync o open gpo6/ovvsync o open
data sheet s15082ej4v0ds 16 pd61051, 61052 2. feature overview the functions and i/o interfaces are set using firmware. supported functions differ depending on firmware. 2.1 video this lsi can do flexible encoding and transcoding by usin g the firmware control of internal cpu and an exclusive use circuit. ntsc/pal video format, which is possible of the encoding is as in table 2-1 . ntsc/pal video format of the transcoding is under 720 dots by 480/576 line/frame. table 2-1. video format mpeg2 mpeg1 video format yes no 720 dots by 480/576 line/frame yes no 704 dots by 480/576 line/frame yes no 544 dots by 480/576 line/frame yes no 480 dots by 480/576 line/frame yes no 352 dots by 480/576 line/frame yes yes 352 dots by 240/288 line/frame 2.1.1 encoding it encodes the video that was converted from the 4:2:2 format into the 4:2: 0 format in the video input/output unit with mpeg2 standard mp@ml, sp@ml and t he mpeg1 standard. it is encoding in variable bit rate (single path vbr encoding) or constant bit rate (cbr). the pre anal ysis supports high quality picture encoding. encode supports frame structure. ? using the following, only 64 mbits sdram is needed. encoding with locally decoding and/ or time base corrector (tbc) pal encoding dvd encoding needs equal to 128 mbits sdram area. the motion estimation size p picture: 128 dots (h) by 64 lines (v) b picture: 96 dots (h) by 48 lines (v), 64 dots (h) by 32 lines (v) i/p picture period in mp@ml : m 3 dual prime estimate, only at the time of m = 1. 2.1.2 transcoding it transcodes the stream of mpeg2 standard mp@ml based. it is possible for the bit rate conversion.
data sheet s15082ej4v0ds 17 pd61051, 61052 2.1.3 input/output processing (1) video input the video input format is itu-r bt.656 (8-bit y/cb/cr t he 4:2:2 format) and 8-bit y/cb/cr which deals with the 4:2:0 format. the horizontal synchronization signal, the ve rtical synchronization signal and the field index can be used without using sav and eav. in this case, ivfld can be used by taking with ivvsync or it judges a field judgment in the polarity of ivhsync behind the falling edge two clock of ivvsync. it judges that an odd field is 'h' and an even field is 'l'. ivvsync and ivhsync need the high / low period more than 3 ivclk. the video-input unit watches over the synchronization signals and detects synchronous error. (2) picture size conversion filter for adapting to the bit rate of the stream, the picture si ze of the encoding can be changed. in addition, picture size changed with the external filter to t he 4:2:0 format can be inputted directly, too. table 2-2. input vi deo data arrangement format line data arrangement 4:2:2 odd/even lines cb0, y0, cr0, y1, cb1, y2, cr1, y3, cb2, y4, cr2, y5, ? 4:2:0 odd lines cb0, y0, cr0, y1, cb1, y2, cr1, y3, cb2, y4, cr2, y5, ? even lines (-), y0, (-), y1, (-), y2, (-), y3, (-), y4, (-), y5, ? (3) time base corrector (tbc) it has a frame-type tbc. it is possible to make stabl e encoding of the channel changing and the nonstandard video signal such as vtr. when using tbc, it needs ov er 64 mbits sdram. the following video signals can be corrected. table 2-3. correctable video signals horizontal sync vertical sync ntsc 1626 to 1806 ivclk/h 246 to 278 h/v pal 1628 to 1828 ivclk/h 294 to 330 h/v remark ivclk: 27 mhz (4) noise reduction respectively the noise reduction of the luminance si gnal and the color signal can be set three levels (5) slicer slicer decodes the luminance signal to the vertical bl anking data. it detects vbid, closed caption, and wide screen signal. the host cpu can read, and stop encoding and re-write the copy control information in vbid and the wide screen signal, on the host cpu interface.
data sheet s15082ej4v0ds 18 pd61051, 61052 table 2-4. slicer tv method vbi data detection line ntsc vbid 20, 283 closed caption 21, 284 pal wide screen signal 23 (336) (6) video output it converts an input video or a local-decoded video into picture size of 720 dots by 480/576 line and outputs with the itu-r bt.656 format. horizontal and vertical synchronization signals are switched from gpo. field detection is easy due to vertical synchronization signal delays 4vclk since horizontal synchronization signal. figure 2-1. video output (a) odd field ovvsync (pal) ovhsync ovvsync (ntsc) 3h 2.5h ovhsync ovclk ovvsync 4ovclk (b) even field ovvsync (pal) ovhsync ovvsync (ntsc) 3h 2.5h h/2+4 ovclk
data sheet s15082ej4v0ds 19 pd61051, 61052 2.2 audio this lsi encodes the mpeg audio encodin g and transcode with the internal dsp. 2.2.1 encoding it encodes mpeg1 audio layer 2 or dolby digital consumer encoder (only the pd61052). in addition, it is possible to bypass internal audio encode dsp, when the audi o elementary stream is encoded by an external audio encoder are inputted. 2.2.2 transcoding (demux, mux) it is possible to multiplex two de-multiplexed audio st reams. it analyzes mpeg1 audi o stream, and extracts the information to multiplex an d notify to the host cpu. 2.2.3 input/output processing two pcm audio signals can be inputted to the audio input interface and the audio inpu t-output interface. when inputting two audio signals, an audio signal is encoded, and another one bypasses the audio encoding dsp, and transfers to the multiplexer. when inputting an audio elem entary stream that has been en coded by the external audio encoder and pcm audio, it can mult iplex two audio elementary streams. the pcm audio or the audio elementary stream can be outputted from the audi o input-output interface. the audio clock (amclk) types the clock by which a phase was locked up stc clock (stclk). table 2-4. audio input/output item input/output format data length 16 bits, 20 bits, 24 bits sampling frequency 32 khz, 44.1 khz, 48 khz justification of transfer msb first i 2 s compatible/left justified/right justified format pcm audio, iec60958 based
data sheet s15082ej4v0ds 20 pd61051, 61052 figure 2-2. audio input (a) msb first right justified mode don't care msb iabd (oabd) iabck (oabck) ialrck (oalrck) lsb lch 16/32 iabck (oabck) rch msb lsb don't care audio data (b) msb first left justified mode lch rch lsb msb msb lsb iabd (oabd) iabck (oabck) ialrck (oalrck) 16/32 iabck (oabck) audio data (c) i 2 s mode lch rch lsb msb msb lsb iabd (oabd) iabck (oabck) ialrck (oalrck) 32 iabck (oabck) audio data
data sheet s15082ej4v0ds 21 pd61051, 61052 figure 2-3. audio output (a) msb first right justified mode msb oabd oabck oalrck lsb lch rch msb msb audio data 16/32 oabck msb lsb (b) msb first left justified mode oabd oabck oalrck lch rch audio data 16/32 oabck lsb msb msb lsb (c) i 2 s mode oabd oabck oalrck lch rch audio data 32 oabck lsb msb msb lsb
data sheet s15082ej4v0ds 22 pd61051, 61052 2.3 mpeg system processing this lsi multiplexes and/or de-multiplexes audio and video streams based on mpeg2-ts/ps and mpeg1. by combining the multiplexer and de-multiplexer, it does the transcode which is accompanied by mpeg2-ts ? mpeg2 ps conversion. 2.3.1 system time clock (1) encoding system when the encoding system operates, it uses the clock input to stclk that is generated with the 27 mhz oscillator. audio master clock is made with 27 mhz of stclk, and then audio synchronizes to stc. figure 2-4. system time clock input (encoding system) pd61051/61052 video decoder xtal pwm ivclk amclk sclk stclk pll ivin7 to ivin0 27 mhz audio in 27 mhz 27 mhz 27 mhz audio adc
data sheet s15082ej4v0ds 23 pd61051, 61052 (2) encoding and transcoding system it can output the signal, which generates the pulse wi de modulation (pwm) with co mparing pcr/scr of the stream and system time clock value, for making the reference clock of the system. figure 2-5. system time clock input (encoding and transcoding system) pd61051/61052 video decoder xtal pwm ivclk amclk sclk stclk vco filter pll ivin7 to ivin0 os is 27 mhz audio in 27 mhz 27 mhz 27 mhz audio adc 2.3.2 multiplex it stamps scr, pcr, dts and pts after multiplexing st reams that are from the vi deo encoder and the audio encoder based on mpeg2-ts/ps. partial ts can be made by forming sit packe t from psi and si data of base on dvb. it is possible to multiplex the packet that inputted from the host cpu interface. 2.3.3 de-multiplex (1) mpeg2-ts using the pid filter corresponding to 16 pids, it separ ates mpeg2-ts to one video stream, two audio streams, and two user data streams. internal cpu extrac ts section data in psi and si of base on dvb. (2) mpeg2-ps with the stream id filter, it separates mpeg2-ps to one video stream , one audio stream, and two user data streams.
data sheet s15082ej4v0ds 24 pd61051, 61052 (3) vbi data the user data stream, the wide screen signal, the closed caption, vbid and format of the video and the audio can be read from the host cpu interface. 2.3.4 transcode the transcode is a combined multiplexer and de-multiplexe r. mpeg2-ts/ps separates into a video stream, two audio streams, and two user data streams. the video stream and the audio str eam are multiplexed to mpeg2-ts/ps after transcode on the elementary. pcr, scr, pts and dts are corrected when multiplexing. in the transcode of mpeg2-ts, it can generate partial ts using the data detect ed by the pid filter and the section filter. figure 2-6. transcode stream stream mpeg2-ts/ps de-multiplexer mpeg2 video bit rate conversion audio es stream buffer audio es stream buffer mpeg2-ts/ps multiplexer the change of the mpeg syst em layer is shown below. mpeg2-ts ? mpeg2-ts mpeg2-ts ? mpeg2-ps mpeg2-ps ? mpeg2-ts mpeg2-ps ? mpeg2-ps mpeg1 ? mpeg1
data sheet s15082ej4v0ds 25 pd61051, 61052 2.4 stream interface when it inputs mpeg2-ts, it is able to con nect parallel data or serial data with the pd61051/61052. when it inputs mpeg2-ps, it should c onnect parallel data with the pd61051/61052. 2.4.1 parallel steam data interface this lsi connects to external device by the master mode or the slave mode. w hen parallel interface, the maximum stream input rate is 100 mbps, the maximum stream output rate is 30 mbps. t he stream of mpeg encoding and transcode is limited to 15 mbps on mpeg mp@ml. (1) stream input it is possible to receive 4 bytes data afte r invalid of isreq of the stream input. remark isstb and isclk are identical pins. figure 2-7. parallel stre am receiving mode (1/2) (a) example for receiving of mpeg2-ts no recei- ved data valid data valid data valid data valid data valid data valid data valid data valid data valid data 1st valid data isvld isclk is7 to is0 issync 1 packet (188 bytes) release in a ts packet no received data isclk shall be under 13.5 mhz.
data sheet s15082ej4v0ds 26 pd61051, 61052 figure 2-7. parallel stre am receiving mode (2/2) (b) example of receiving mpeg 2-ps, es with valid and clock valid data valid data valid data valid data valid data valid data valid data valid data no recei- ved data no recei- ved data no recei- ved data no recei- ved data isclk is7 to is0 issync no received data isreq isvld don't care it is possible to receive till 4 bytes (c) example of receiving mpeg2-ps, mpeg2-es with a strobe valid data valid data valid data valid data valid data valid data valid data valid data no recei- ved data no recei- ved data no recei- ved data no recei- ved data isreq isstb is7 to is0 issync no received data don't care it is possible to receive till 4 bytes (2) stream output there are two modes: valid operation master mode and strobe operati on byte transfer mode. the appropriate transfer mode for the system can be sele cted by setting the two str eam output mode and transfer rate. remark osstb and osrdy are the same pins as osclk and osvld, respectively. operation can be selected using combinations of o sstb and osrdy or osclk and osvld.
data sheet s15082ej4v0ds 27 pd61051, 61052 (a) master mode valid this is the mpeg2-ts dedicated output mode. the period of osclk can be selected from n times 37 ns (1/27 mhz) (3 n 255, n is an integer). if using local decode or input video display, the period is 4 n 255 (n is an integer). figure 2-8. parallel stream transm ission mode ; transmission of mpeg 2-ts (packet length is 188 bytes) (a) master mode, valid valid data valid data valid data valid data valid data valid data valid data valid data valid data 1st valid data osvld osclk os7 to os0 ossync invalid invalid invalid 1 packet (188 bytes) (b) the transfer condition from reset osvld reset osclk ossync os7 to os0 unsettled unsettled unsettled the setting of an interface mode the stream preparation completion unsettled (data does not change)
data sheet s15082ej4v0ds 28 pd61051, 61052 (b) bytes transfer mode, strobe in byte transfer mode, the transfer rate is determined by the handshake of osreq and osstb. figure 2-9. parallel stream transmission mode (transmission of mpeg2-ps, mpeg2-es) (a) example for transmission of st robe mode one byte transfer osrdy osreq osstb os7 to os0 ossync (b) the transfer condition from reset osrdy reset osreq ossync os7 to os0 unsettiled unsettiled the setting of an interface mode the stream preparation completion unsettled (data does not change) osstb unsettiled
data sheet s15082ej4v0ds 29 pd61051, 61052 2.4.2 serial stream data interface this lsi is able to input a serial stream. bit rate of serial input is limited less than paralle l interface. serial stream interface can transfer only mpeg2-ts stream. maximum bit ra te of stream input is less then 64 mbps. bit rate of stream out is 27 mbps. additionally, encoding and trans coding bit rate is limited to 15 mbps on mpeg2 mp@ml. (1) stream input isclk is input by less than 64 mhz clo ck. data is msb first. issync should active while first byte each packet. if packet error occurred, iserr should active from issync of the packet. isvld should valid while each byte. isvld shall invalid while 8 bits between each packets.
data sheet s15082ej4v0ds 30 pd61051, 61052 figure 2-10. serial stream input isclk is0 isvld is1/iserr msb issync bit1 bit6 bit0 msb first byte of ts packet one packet more than 8 isclk msb invalid bit0 isclk is0 isvld is1/iserr "l" issync msb lsb msb lsb msb lsb msb remark example for isvld, issync, iserr active high, isclk active high edge
data sheet s15082ej4v0ds 31 pd61051, 61052 (2) stream output osclk is fixed 27 mhz ossync active at first byte in eac h packet. osvld is active of 1 packet continuously. data is the msb first outputs. issync becomes active among 1 byte at the head of the packet. figure 2-11. serial stream output osclk os0 osvld msb ossync bit1 bit6 bit0 msb first byte of ts packet one packet more than 8 isclk msb invalid bit0 osclk os0 osvld ossync msb lsb msb lsb msb lsb msb remark example for osvld, ossync, oserr active high
data sheet s15082ej4v0ds 32 pd61051, 61052 2.5 host cpu interface the connection of the host cpu can select the eight bits parallel data interface and serial interface (spi). internal cpu sends and receives command status through the system interface register , which is in the host cpu interface unit. in addition, to control an internal dma controller thro ugh the system interface register , it loads an instruction for internal cpu to the instruction ram and the transfer of the large-volume data c an be sent to the dat a area on sdram. figure 2-12. host cpu interface host cpu system interface register instruction ram of internal cpu internal cpu sdram interface sdram dma controller pd61051/61052 the following describes loading of internal cpu instruction. (1) parallel interface when parallel interface is selected, host interface has 6-bit address, 8-bit data bus and control ports. cwait is selected with cmode1 to wait on ready signa l mode, cmode1 selects active polarity of cwait. (2) serial interface the pd61051/61052 communicates with the host cpu using the spi (serial peripheral interface) serial bus. the host cpu becomes a bus master. the low edge of the chip selection is communication beginning. its high edge is communication ending. an address and the reading / writing mode are shown at t he first byte after the chip selection becomes low. it is the msb first of six bits of addresses, eight bits of data. fix csclk to high level during ccs is disabled (high level). the pd61051/61052 becomes a master and downloads the instru ction of the internal cpu from external rom. csclk: the serial clock csdi: the data input csdo: the data output ccs: the chip selection
data sheet s15082ej4v0ds 33 pd61051, 61052 figure 2-13. serial interface a5 a4 a3 a2 a1 a0 w x d5 d4 d3 d2 d1 d0 d7 d6 xx x a5 a4 a3 a2 a1 a0 r x x x xxxxx x xx x xx d5 d4 d3 d2 d1 d0 d7 d6 [data write] [data read] ccs csclk csdi csdo ccs csclk csdi csdo xx 2.6 sdram interface external memory is sdram. it is possible to use the following. table 2-6. use memory memory data bus width quant ity use memory capacity 16 mbit sdram 16 bits 2 32 mbits 64 mbit sdram 32 bits 1 64 mbits 64 mbit sdram 16 bits 2 128 mbits 128 mbit sdram 16 bits 2 128 mbits 128 mbit sdram 32 bits 1 128 mbits the pd61051/61052 preserves the part of t he parameter that is necessary to generate the stream, entry video image, a video stream, an audio stream, a stream header, user dat a, and the instruction of the firmware at this memory. this system uses only cas latency = 3, burst length = 4. when encode using time base corrector and/or displays lo cal decoding picture, it needs equal to or more than 64 mbits sdram. when pal encoding, it needs equal to or more than 64 mbit sdram. when transcoding, it needs equal to or more than 64 mbit sdram.
data sheet s15082ej4v0ds 34 pd61051, 61052 2.7 memory connection diagram each memory connection is as follows. figure 2-14. memory connection diagram (1/2) (a) 16 mbit sdram by 2 a11 a10 to a0 d15 to d0 1 mbits16 sdram a11 ma13 pd61051/61052 bank a: sdram address = 0x xxxx xxxx xxxxb bank b: sdram address = 1x xxxx xxxx xxxxb ma12 ma11 ma10 to ma0 md31 to md16 md15 to md0 a10 to a0 d15 to d0 1 mbits16 sdram (b) 64 mbit sdram by 1 a12 a11 ma13 pd61051/61052 bank a: sdram address = 00 xxxx xxxx xxxxb bank b: sdram address = 10 xxxx xxxx xxxxb bank c: sdram address = 01 xxxx xxxx xxxxb bank d: sdram address = 11 xxxx xxxx xxxxb ma12 ma11 ma10 to ma0 md31 to md16 md15 to md0 a10 to a0 d31 to d16 d15 to d0 2 mbits32 sdram
data sheet s15082ej4v0ds 35 pd61051, 61052 figure 2-14. memory connection diagram (2/2) (c) 64 mbit sdram by 2 or 128 mbit sdram by 2 d15 to d0 4 mbits16 sdram a13 a12 a11 ma13 pd61051/61052 bank a: sdram address = 00 xxxx xxxx xxxxb bank b: sdram address = 10 xxxx xxxx xxxxb bank c: sdram address = 01 xxxx xxxx xxxxb bank d: sdram address = 11 xxxx xxxx xxxxb ma12 ma11 ma10 to ma0 md31 to md16 md15 to md0 a10 to a0 ma13 ma12 ma11 ma10 to ma0 d15 to d0 4 mbits16 sdram
data sheet s15082ej4v0ds 36 pd61051, 61052 2.8 memory map firmware sets memory map such as video image area and usable work area. firmware cabinet (temporal buffered area) is the area which firmware does not use. video image area size is changed ntsc or pal. each area are changed by the firmware. figure 2-15. memory map (1/2) (a) 16 mbit sdram by 2 00000h bank a video stream audio stream user data 0 header firmware firmware firmware 7ffffh bank b video stream video image area (b) example for 64 mbit sdram by 1 00000h bank a video stream 0 audio stream 0 user data 0 header unused audio stream 1 user data 1 7ffffh 7ffffh 00000h bank b video stream 0 video image area bank c video stream 1 bank d video stream 1 instruction pool instruction pool usable work area usable work area video image area firmware firmware firmware firmware firmware
data sheet s15082ej4v0ds 37 pd61051, 61052 figure 2-15. memory map (2/2) (c) example for 64 mbit sdram by 2 or 128 mbit sdram by 2 00000h bank a video stream unused header fffffh 00000h 80000h fffffh bank b video stream bank c unused bank d unused audio stream audio stream video stream video stream user data 0 user data 1 instruction pool instruction pool unused unused usable work area usable work area video image area firmware firmware firmware firmware video image area
data sheet s15082ej4v0ds 38 pd61051, 61052 3. system interface register this lsi corresponds to the various operation modes in exchange instruction of internal cpu from sdram to instruction ram (iram). this has 64 byte registers. they are defined to common registers, interr upt registers and interrupt mask registers. when there is access in the same address from both of the inte rnal cpu and the host cpu, the later data is left at the register. also, when the writing occurs to the same address at t he same time about the common register, the data of the host cpu is left at the register figure 3-1. system interface register host cpu system interface register instruction ram of internal cpu internal cpu sdram interface sdram dma controller pd61051/61052
data sheet s15082ej4v0ds 39 pd61051, 61052 3.1 register mapping (general mapping) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 00h to 1fh defined by firmware r/w 20h si ssd sdi msd mi sdw sdr r/w download mode 21h sa19 to sa16 r/w source address 22h sa15 to sa8 r/w source address 23h sa7 to sa0 r/w source address 24h da16 r/w destination address 25h da15 to da8 r/w destination address 26h da7 to da0 r/w destination address 27h tc18 to tc16 r/w transfer data count 28h tc15 to tc8 r/w transfer data count 29h tc7 to tc0 r/w transfer data count 2ah icpu-int r/w int. to internal cpu 2bh dma- err-m dma- rdy-m dma- done-m r/w interrupt mask0 2ch defined by firmware r/w interrupt mask1 2dh defined by firmware r/w interrupt mask2 2eh defined by firmware r/w interrupt mask3 2fh defined by firmware r/w interrupt mask4 30h dma-err dma-rdy dma- done r/w interrupt0 31h defined by firmware r/w interrupt1 32h defined by firmware r/w interrupt2 33h defined by firmware r/w interrupt3 34h defined by firmware r/w interrupt4 35h irom2 to irom0 r/w mask rom cycle 36h isreq osvld r/w port setup 37h to 3dh 3eh nbr all reset r/w reset 3fh td7 to td0 r/w transfer data
data sheet s15082ej4v0ds 40 pd61051, 61052 3.2 register functions 3.2.1 common register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 00h to 1fh defined by firmware r/w each firmware defines these registers. these registers are used to communicate with host cpu and internal cpu. for the details of the register, refer to the application notebook. the reset of the reset pin or all r eset of the reset register initializes addresses 00h and 01h addresses to 0h. the original value of the other register is unsettled. it keeps a setting value before reset. 3.2.2 data transfer register these registers are defined data transfer such as host cpu sdram, sdram host cpu, host cpu iram of internal cpu, sdram iram of internal cpu and instruction rom iram of internal cpu. the host cpu transfers with sdram via had a transfer buffer of 128 bytes on this lsi. the transfer with the instru ction ram becomes 4 bytes. a transfer error occurs if the transfer mode register, so urce address register, destination address register, or transfer counter register is changed before releasing the transfer mode register following transfer completion after setting the transfer mode register and starting the transfer. when tr ansferring data as follows: host cpu instruction ram of internal cpu, host cpu sdram, sdram instruction ram of internal cpu, instruction rom sdram, instruction rom instruction ram of internal cpu, execute a software reset of the internal cpu (address 3eh 02h) before transfer and release the reset after transfer.
data sheet s15082ej4v0ds 41 pd61051, 61052 (1) data transfer register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 20h si ssd sdi msd mi sdw sdr r/w download mode bit field function initial value 7 si host cpu instruction ram of internal cpu 0: releasing of transfer, 1: transfer note 0 6 ssd host cpu sdram 0: releasing of transfer, 1: transfer note 0 5 sdi sdram instruction ram of internal cpu 0: releasing of transfer, 1: transfer note 0 4 msd instruction rom sdram 0: releasing of transfer, 1: transfer note 0 3 mi instruction rom instruction ram of internal cpu 0: releasing of transfer, 1: transfer note 0 2 reserved (set only 0) 0 1 sdw host cpu sdram 0: releasing of transfer,1: transfer 0 0 sdr sdram host cpu 0: releasing of transfer, 1: transfer 0 note set internal cpu reset (with register 3eh 02h) more than one bit cannot be set to 1 at the same time. it becomes a transfer error when writing at the transfer mode register while transferring. when canceling a transfer wh ile transferring, it stops a tr ansfer. at this time, the data in the transfer buffer becomes inva lid. the transfer of sdr with once is to a maximum of 128 bytes. if host cpu stops the transfer, host cpu should operate transfer error handling.
data sheet s15082ej4v0ds 42 pd61051, 61052 (2) source address register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 21h sa19 to sa16 r/w source address 22h sa15 to sa8 r/w source address 23h sa7 to sa0 r/w source address it sets the address of the data to transfer. it becomes effect ive in case of transfer from sdram or instruction rom. until it releases a transfer mode after setting a transfer m ode register, it isn't possible to change. the transfer error occurs when rewriting this register before releasing a tr ansfer mode. the relation wi th the address of sdram, external instruction rom is shown in figure 3-2 and 3-3 . the addressing of sdram becomes a 32 address by 4-word unit (128 bytes). the relation with the sdram bank and address is shown in table 3-1 . figure 3-2. relation of so urce address and sdram address 0000 00000 sdram address host cpu interface register 21h to 23h the pd61051/61052 adds 0 automatically sa19 sa18 sa17 sa16 sa11 sa10 sa9 sa8 sa15 sa14 sa13 sa12 a19 a18 a17 a16 a21 a20 a11 a10 a9 a8 a15 a14 a13 a12 a7 a6 a5 sa3 sa2 sa1 sa0 sa7 sa6 sa5 sa4 bank select figure 3-3. relation of source addre ss and external instruction rom address 0000 extemal instruction rom address host cpu interface register 21h to 23h sa19 sa18 sa17 sa16 sa11 sa10 sa9 sa8 sa15 sa14 sa13 sa12 fa19 fa18 fa17 fa16 fa11 fa10 fa9 fa8 fa15 fa14 fa13 fa12 fa3 fa2 fa1 fa0 fa7 fa6 fa5 fa4 sa3 sa2 sa1 sa0 sa7 sa6 sa5 sa4 table 3-1. relation of sdram bank and address memory bank a bank b bank c bank d 16 mbit sdram by 2 000000h to 07ffffh 200000h to 27ffffh - - 16 mbit sdram by 1 000000h to 07ffffh 200000h to 27ffffh 100000h to 17ffffh 300000h to 37ffffh 64 mbit sdram by 2 128 mbit sdram by 1 128 mbit sdram by 2 000000h to 0fffffh 200000h to 2fffffh 100000h to 1fffffh 300000h to 3fffffh 128 mbit sdram by 1 000000h to 0fffffh 200000h to 2fffffh 100000h to 1fffffh 300000h to 3fffffh
data sheet s15082ej4v0ds 43 pd61051, 61052 (3) destination address register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 24h da16 r/w destination address 25h da15 to da8 r/w destination address 26h da7 to da0 r/w destination address it sets destination address. it becomes effective in case of transfer to sdram or instruction ram of internal cpu. it isn't possible to change until it cancels a transfer mode a fter setting a transfer mode register. it becomes a transfer error when rewriting before canceling a transfer mode. t he relation of the address of sdram and instruction ram of internal cpu is as in figure 3-4 and 3-5 . the addressing of sdram becomes a 32 address by 4-word unit (128 bytes). figure 3-4. relation of dest ination address and sdram address 0000000 00000 sdram address host cpu interface register 24h to 26h bank select the pd61051/61052 adds 0 automatically da16 da11 da10 da9 da8 da15 da14 da13 da12 a19 a18 a17 a16 a21 a20 a11 a10 a9 a8 a15 a14 a13 a12 a7 a6 a5 da3 da2 da1 da0 da7 da6 da5 da4 figure 3-5. relation of destination address a nd instruction rom addr ess of internal cpu 0000000 instruction ram address of intemal cpu host cpu interface register 24h to 26h da16 da11 da10 da9 da8 da15 da14 da13 da12 a11 a10 a9 a8 a14 a13 a12 a3 a2 a1 a0 a7 a6 a5 a4 da3 da2 da1 da0 da7 da6 da5 da4
data sheet s15082ej4v0ds 44 pd61051, 61052 (4) transfer data counter register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 27h tc18 to tc16 r/w transfer data count 28h tc15 to tc8 r/w transfer data count 29h tc7 to tc0 r/w transfer data count it sets the transfer data number of the bytes. in case of transfer between host cpu and sdram, it sets the number of the transfer bytes by 4 bytes unit. in case of transfer from instructions rom, sdram host cpu to the in struction ram of internal cpu, it sets the number of the transfer bytes /4 by the 4 byte unit. (5) transfer data register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 3fh td7 to td0 r/w transfer data this register is transfer data window. figure 3-6. sdram write byte3 byte7 byte19 byte11 byte15 byte2 byte6 byte18 byte10 byte14 byte1 byte5 byte17 byte9 byte13 byte0 byte4 byte16 byte8 byte12 byte0 byte1 byte4 byte2 byte3 byte7 byte8 byte5 byte6 td7 to td0 sdram lower byte first host cpu write transfer buffer (128 bytes) sdram address = da16 to da0128 sdram address = da16 to da0128+5
data sheet s15082ej4v0ds 45 pd61051, 61052 sdram read <1> interrupt mask host cpu sets mask bit to interrupt mask register (2ch to 2fh) for the in terrupt that needs a data transfer. <2> set source address host cpu sets the address of sdram to the s ource address register (21h to 23h) of the pd61051/61052. <3> set the number (equal to or less than 128 by tes) of the data to read by 4 bytes unit host cpu sets the data number of t he bytes to the transfer data counter register (27h to 29h) of the pd61051/61052. <4> set the transfer of sdram host cpu. host cpu sets 01h to the trans fer mode register (20h) of the pd61051/61052. <5> cint interrupt (interrupt pin) <6> confirms that the interrupt factor and clear interrupt factor host cpu confirms that the inte rrupt register 0 (30h) of the pd61051/61052 becomes 02h or 01h and clears writing a same value of the inte rrupt register 0 (30h) to the interrupt register 0 (30h) of the pd61051/61052. <7> data read host cpu reads data from the number of times with the set number of bytes, the transfer data register (3fh) of the pd61051/61052. <8> cint interrupt (interrupt pin) <9> confirm the interrupt factor host cpu confirms that the inte rrupt register 0 (30h) of the pd61051/61052 becomes 01h. (it clears a writing interrupt factor in 01h at the interr upt register 0 (30h) register of the pd61051/61052.) <10> release of sdram host cpu mode host cpu clears a writing interrupt factor in 01h at the interrupt register 0 (30h) register of the pd61051/61052 after setting 00h to the transfer mode register (20h) of the pd61051/61052. <11> release of interrupt mask it releases the limitation on interrupt which set by <1>.
data sheet s15082ej4v0ds 46 pd61051, 61052 sdram write <1> interrupt mask host cpu sets mask bit to interrupt mask register (2ch to 2fh) for the in terrupt that needs a data transfer. <2> set destination address host cpu sets the address of sdram to the desti nation address register (24h to 26h) of the pd61051/61052. <3> set the number of the data to write by a 4 byte unit host cpu sets the data number of the by tes by 4 bytes unit to the transfer data counter register (27h to 29h) of the pd61051/61052. <4> set the transfer of host cpu sdram host cpu sets 02h to the trans fer mode register (20h) of the pd61051/61052. <5> data write host cpu writes data to the trans fer data register (3fh) of the pd61051/61052 at times with more few 128 bytes or transfer data count register setting value. <6> cint interrupt (interrupt pin) <7> confirm the interrupt factor when the number of the transfer data is less then 128 bytes, host cpu confirms that the interrupt register 0 (30h) of the pd61051/61052 becomes 01h, and go to <9>. <8> confirm that next data transfer prepare completed host cpu confirms that the inte rrupt register 0 (30h) of the pd61051/61052 becomes 02h or 01h and clears a writing sane value of the interrupt register 0 (30h) to the inte rrupt register 0 (30h) of the pd61051/61052. return to <5> and next data write. <9> release of sdram host cpu host cpu clears a writing interrupt factor in 01h at the interrupt register 0 (30h) register of the pd61051/61052 after setting 00h to the transfer mode register (20h) of the pd61051/61052. <10> release of interrupt mask it releases the limitation on interrupt which is set by <1>. <11> in the case of an interrupt to internal cpu, it is necessary host cpu sets a data bank number and the number of t he bytes to the address that defined with the firmware. it sets 01h to the 2ah address of the pd61051/61052 and it notifies an in terrupt to internal cpu.
data sheet s15082ej4v0ds 47 pd61051, 61052 3.2.3 internal cpu interrupt register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 2ah icpu-int r/w int. to internal cpu host cpu set interrupt to internal cpu. internal cpu clears this bit after interrupt operation. the reset of the reset pin or a ll reset of the reset register in itializes this address to 0h. 3.2.4 interrupt mask register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 2bh dma-err -m dma-rdy -m dma-don e-m r/w interrupt mask0 2ch defined by firmware r/w interrupt mask1 2dh defined by firmware r/w interrupt mask2 2eh defined by firmware r/w interrupt mask3 2fh defined by firmware r/w interrupt mask4 these registers are interrupt masks fo r next interrupt. interrupt mask c an be set bit by bit. when setting an interrupt mask, cint does not become high ev en if the interrupt register becomes 1. the reset of the reset pin or a ll reset of the reset register in itializes this address to 0h. 3.2.5 download interrupt register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 30h dma-err dma-rdy dma-don e r/w interrupt0 it is set for 1 when the interrupt factor occurs. the interrupt bit clears when host cpu writes to this register after the interrupt processing. the reset of the reset pin or a ll reset of the reset register in itializes this address to 0h. clear processing continues until interrupt registers is cleared. bit field function initial value 7 to 3 reserved (set 0) 2 dma-err data transfer error 0: normal, 1: error 0 1 dma-rdy data transfer prepared 0: normal, 1: transfer 0 0 dma-done data transfer ended 0: normal, 1: transfer ended 0 it outputs dma-rdy or dma-done every 128-byte trans fer. dma-done is output when the transfer ends.
data sheet s15082ej4v0ds 48 pd61051, 61052 3.2.6 interrupt register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 31h defined by firmware r/w interrupt1 32h defined by firmware r/w interrupt2 33h defined by firmware r/w interrupt3 34h defined by firmware r/w interrupt4 it is set for 1 when the interrupt factor occurs. the interrupt bit clears when host cpu writes 1 in t he bit of the interrupt after the interrupt processing. when the other interrupt (which isn't masked) is set to 1 when clearing a interrupt, cint becomes high 1 s later. the reset of the reset pin or a ll reset of the reset register in itializes this address to 0h. clear processing continues until interrupt registers is cleared. address bit field function initial value 31h to 34h 7 to 0 firmware define 0: normal, 1: interrupt 0h 3.2.7 reset register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 3eh nbr all reset r/w reset when the host cpu sets 1 to all reset, it resets the inside and it returns to 0 automatically. the reset of the reset pin or a ll reset of the reset register in itializes this address to 0h. bit field function initial value 7 to 2 reserved (set 0) 1 nbr internal cpu reset 0: normal, 1: reset 0 0 all reset same hardware reset 0: normal, 1: reset 0
data sheet s15082ej4v0ds 49 pd61051, 61052 3.2.8 rom access cycle register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 35h irom2 to irom0 r/w mask rom cycle it specifies the access cycle of the inst ruction rom of internal cpu when c onnecting host cpu interface with the serial bus. the reset of the reset pin or all reset of the reset register initializes this address to 7h. bit field function initial value 7 to 3 reserved (set 0) 2 to 0 irom2 to irom0 access cycle of instruction rom 0: reserved, 1 to 7: (setting value+2) by 24.6 mhz 7h 3.2.9 port setup register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w 36h isreq osvld r/w port setup this register sets the active polarity of isreq and osvl d. the reset of the reset pin or all reset of the reset register initialize s this address to 0h. bit field function initial value 7 to 2 reserved (set 0) 1 isreq active polarity of isreq 0: low active of request, 1: high active of request 0 0 osvld active polarity of osvld/osrdy 0: low active of valid/ready 1: high active of valid/ready 0
data sheet s15082ej4v0ds 50 pd61051, 61052 4. system interface procedure the host cpu transfers the firmware of each operation mode to the instruction ram of the internal cpu and works it. this lsi stores up firmware in sdram. host cpu sets to load the firmware of each operation mode in the instruction ram of internal cpu from sdram. when using a parallel bus interface for the host cpu interfac e, the host cpu sets a data transfer register after hardware reset and transfers the initializat ion program of sdram to instruction ra m of internal cpu and executing. host cpu writes firmware to sdram. when using a serial bus interface for the host cpu interf ace, the host cpu sets a data transfer register after hardware ware reset and transfers the in itialization program of sdram to inst ruction ram of internal cpu from external instruction rom and executing. host cpu l oads firmware in sdram from instruction rom outside. it stores the firmware of the encoding and the transcode to sdram from rom in case of start-up of the system, and then it can do the changing of a feature at short time by t he high-speed transfer of sdram. the host cpu sets the mode of the terminal of the pd61051/61052 and the access cycle of rom to the system interface register after hardware reset and sets the transfe r of the instruction of the internal cpu after sdram is initialized.
data sheet s15082ej4v0ds 51 pd61051, 61052 4.1 outline an overview from the reset of the hardware to the setting of an operation mode is shown. y n initialization mode setting mode change operation continuation internal cpu start-up reset address (3eh) 00h hardware reset instruction download sdram initialization note software reset of internal cpu reset address (3eh) 02h internal cpu software reset software reset of internal cpu reset address (3eh) 02h note this is not necessary in case that the sdram initialization firmware is not separated.
data sheet s15082ej4v0ds 52 pd61051, 61052 4.2 firmware download the host cpu downloads the firmware at the instruction ram for the internal cpu. when a host cpu is connected with the serial bus, the fi rmware can be downloaded from the external rom for the download processing to speed up. in addition, it stores more than one piece of firmware in the instruction pool area of sdram and it can be replaced depending on the need, too. when transferring to the instruction ram of the internal cp u, the transfer counter regist er setting value (number of the transfer bytes / 4) is (program size +3)/ 4. 4.2.1 host cpu to instructi on ram of internal cpu host cpu transmits the firmware to in struction ram of the internal cpu. when transferring data continuously, transfer during resetting an internal cpu, if reset of internal cpu is can canceled on the way, the internal cpu sometime malfunction. y n return host cpu to instruction ram of internal cpu internal cpu reset reset register (3eh) 02h setting destination address register (24h to 26h) setting (program size + 3)/4 transfer counter register (27h to 29h) setting host cpu iram transfer transfer mode register (20h) 80h setting transfer data register (3fh) instruction transfer ending (refer to 4.7 ) all instruction written ? internal cpu reset is canceled reset register (3eh) 00h setting
data sheet s15082ej4v0ds 53 pd61051, 61052 4.2.2 external rom to instruction ram of internal cpu when the host cpu is a serial bus type, cpu transmits the instruction of a m ode from external rom to instruction ram of internal cpu. when transferring data continuously, transfer during resetting an internal cpu, if reset of internal cpu is can canceled on the way, the internal cpu sometime malfunction. external rom to instruction ram of internal cpu internal cpu reset reset register (3eh) 02h setting destination address register (24h to 26h) setting source address register (21h to 23h) setting rom access cycle register (35h) setting (program size + 3)/4 transfer counter register (27h to 29h) setting irom iram transfer transfer mode register (20h) 80h setting return transfer ending (refer to 4.7 ) internal cpu reset is canceled reset register (3eh) 00h setting
data sheet s15082ej4v0ds 54 pd61051, 61052 4.2.3 host cpu to sdram the host cpu can store firmware in the instruction pool area of sdram for the internal cpu. it stores more than one piece of firmware and it can be replaced depending on the need, too. when transferring data continuously, transfer during resetting an internal cpu, if reset of internal cpu is can canceled on the way, the internal cpu sometime malfuncti on. the number of the transfer bytes is a 4-byte unit. y y y y n n n n instruction download destination address register (24h to 26h) setting internal cpu reset reset register (3eh) 02h setting number of transefer bytes transfer counter register (27h to 29h) setting host cpu sdram transfer transfer mode register (20h) 40h setting cint? transfer data register (3fh) instruction interrupt register 0 (30h): (02h or 01h) y n interrupt register 0 (30h): 04h interrupt register 0 clear interrupt register 0 (30h) interrupt register 0 (30h) all instruction writing ending? 128 bytes writing ending? return transfer error handling (refer to 4.8 ) return transfer ending (refer to 4.7 ) internal cpu reset is canceled reset register (3eh) 00h setting
data sheet s15082ej4v0ds 55 pd61051, 61052 4.2.4 external rom to sdram the firmware for the internal cpu can be stored in the fi rmware cabinet of sdram from the external rom. it stores more than one piece of firmware beforehand an d it can be replaced according to need, too. when transferring data continuously, transfer during resetting an internal cpu, if reset of internal cpu is can canceled on the way, the internal cpu sometime malfunction. when transferring data below the 1k-byte, transfer, dividing every 128 bytes. the number of the transfer bytes is a 4-byte unit. (a) transfer over 1 kbytes (b) transfer below 128 bytes instruction download (serial bus) destination address register (24h to 26h) setting source address register (21h to 23h) setting internal cpu reset reset register (3eh) 02h setting number of transfer bytes /4 transfer counter register (27h to 29h) setting after 70 sec clear mask transfer interrupt interrupt mask0 (2bh) 00h irom sdram transfer transfer mode register (20h) 10h setting interrupt mask0 (2bh) 0 3h setting transfer ending (refer to 4.7 ) return internal cpu reset is canceled reset register (3eh) 00h setting instruction download (serial bus) destination address register (24h to 26h) setting source address register (21h to 23h) setting internal cpu reset reset register (3eh) 02h setting number of transfer bytes /4 transfer counter register (27h to 29h) setting irom sdram transfer transfer mode register (20h) 10h setting transfer ending (refer to 4.7 ) return internal cpu reset is canceled reset register (3eh) 00h setting
data sheet s15082ej4v0ds 56 pd61051, 61052 4.3 sdram write during executing while encoding, the host cpu can transfer parameters to the internal cpu through sd ram. the number of the transfer bytes is a 4-byte unit. y n n sdram writing, during executing mask interrupt which requests data transfer interrupt mask register (2ch to 2fh) setting clear mask interrupt which requests data transfer interrupt mask register (2ch to 2fh) setting destination address register (24h to 26h) setting number of transfer bytes transfer counter register (27h to 29h) setting host cpu sdram transfer transfer mode register (20h) 02h setting return transfer data register (3fh) data all data writing ending? 128 bytes writing ending? transfer ending (refer to 4.7 ) clear mask interrupt which requests data transfer interrupt mask register (2ch to 2fh) setting return transfer error handling (refer to 4.8 ) y y y n n cint? interrupt register 0 (30h): (02h or 01h) y n interrupt register 0 (30h): 04h interrupt register 0 clear interrupt register 0 (30h) interrupt register 0 (30h)
data sheet s15082ej4v0ds 57 pd61051, 61052 4.4 sdram read during executing while encoding, the host cpu reads par ameters of usable work area of sdram. the maximum data of the reading once is 128 bytes. when reading is equal to or more than 128 byte data, execute reading processing repeatedly. the number of the transfer bytes is a 4 bytes unit. sdram reading, during executing mask interrupt which requests data transfer interrupt mask register (2ch to 2fh) settin source address register (21h to 23h) setting transfer data register (3fh) read data number of transfer bytes transfer counter register (27h to 29h) setting sdram host cpu transfer transfer mode register (20h) 01h setting clear mask interrupt which requests data transfer interrupt mask register (2ch to 2fh) setting return transfer error handling (refer to 4.8 ) clear mask interrupt which requests data transfer interrupt mask register (2ch to 2fh) setting return transfer ending (refer to 4.7 ) y n y n cint? n all instructions reading ending? interrupt register 0 (30h): (02h or 01h) yy n interrupt register 0 (30h): 04h interrupt register 0 clear interrupt register 0 (30h) interrupt register 0 (30h)
data sheet s15082ej4v0ds 58 pd61051, 61052 4.5 sdram initialization the host cpu transfers the firmware which makes sdram a standby condition to the instruction ram of the internal cpu and executes it. n y y n return sdram initialization sdram initialize firmware to instruction ram of internal cpu release of software reset of internal cpu reset register (3eh) 00h 100 s wait interrupt register x initialization ending interrupt release cint? interrupt register x initialization ending
data sheet s15082ej4v0ds 59 pd61051, 61052 4.6 operation mode setting by changing firmware when changing a mode, host cpu transfe rs the instruction of each mode from sdram to the instruction ram of the internal cpu and restarts. return mode setting software reset of internal cpu reset register (3eh) 02h source address register (21h to 23h) setting destination address register (24h to 26h) setting number of transfer bytes/4 transfer counter register (27h to 29h) setting sdram iram transfer transfer mode register (20h) 20h setting parameter setting transfer ending (refer to 4.7 ) internal cpu reset is canceled reset register (3eh) 00h setting y y n n n y parameter setting mode setting a mode setting a destination address register (24h to 26h) setting system interface register setting number of transfer bytes transfer counter register (27h to 29h) setting host cpu sdram transfer transfer mode register (20h) 40h setting transfer data register (3fh) parameter all parameters writing ending? all parameters in sdram writing ending? 128 bytes writing ending? return transfer ending (refer to 4.7 ) y y n n cint? interrupt register 0 (30h): (02h or 01h) y n interrupt register 0 (30h): 04h interrupt register 0 clear interrupt register 0 (30h) interrupt register 0 (30h) return transfer error handling (refer to 4.8 )
data sheet s15082ej4v0ds 60 pd61051, 61052 4.7 transfer ending the host cpu confirms a transfer error when the instruction or data transfer ends. the host cpu clears transfer m ode and interrupt registers. transfer ending interrupt register 0 clear interrupt register 0 (30h) 01h transfer mode register (20h) 00h setting return transfer error handling (refer to 4.8 ) y y n n cint? interrupt register 0 (30h): 01h y n interrupt register 0 (30h): 04h
data sheet s15082ej4v0ds 61 pd61051, 61052 4.8 transfer error handling 4.8.1 transfer error handling 1 it is the error handling of dma-err which occurs when interrupting the transfers (the host cpu the instruction ram of internal cpu transfer, the host cpu sdram transfer (ssd, sdw), the external rom sdram transfer and the external rom the instruction ram of internal cpu transfer) transfer error handling 1 host cpu sdram transfer release transfer mode register (20h) 00h setting set destination address register (24h to 26h) to unused area of sdram host cpu sdram transfer transfer mode register (20h) 02h setting interrupt register 0 (30h) 01h setting transfer counter register (27h to 29h) 04h setting transfer data register (3fh) dummy data clear the transfer error interrupt register 0 (30h) 04h setting return y y n n cint? interrupt register 0 (30h): 01h y n all data writing ending?
data sheet s15082ej4v0ds 62 pd61051, 61052 4.8.2 transfer error handling 2 this is a error handling of dma-err which occurs when interrupting the transfers (s dram read during executing and sdram instruction ram of internal cpu transfer) transfer error handling 2 sdram host cpu transfer release transfer mode register (20h) 00h setting interrupt register 0 (30h) 01h setting transfer counter register (27h to 29h) 04h setting transfer counter register (27h to 29h) 04h setting transfer data register (3fh) dummy data destination address register (24h to 26h) unusing area setting transfer data register (3fh) data read sdram host cpu transfer transfer mode register (20h) 01h setting host cpu sdram transfer transfer mode register (20h) 02h setting clear interrupt register 0 interrupt register 0 (30h) y y n n cint? interrupt register 0 (30h): 01h y n all data reading ending? y y n n cint? interrupt register 0 (30h): 02 h host cpu sdram transfer release transfer mode register (20h) 00h setting interrupt register 0 (30h) 01h setting transfer data register (3fh) dummy data return y y n n cint? interrupt register 0 (30h): 01h y n all data writing ending? clear transfer error interrupt register 0 (30h) 04h setting n host cpu sdram transfer release transfer mode register (20h) 00h setting y all data writing ending? transfer counter register (27h to 29h) 04h setting destination address register (24h to 26h) unusing area setting host cpu sdram transfer transfer mode register (20h) 02h setting interrupt register 0 (30h) setting
data sheet s15082ej4v0ds 63 pd61051, 61052 4.8.3 transfer error handling 3 it is the error handling of dma-err which occurs when tr ansfer operation in case of host cpu serial connection with spi. transfer error handling 3 sdram host cpu transfer transfer mode register (20h) 01h setting interrupt register 0 (30h) 02h setting transfer counter register (27h to 29h) 01h setting transfer data register (3fh) data read source address register (21h to 23h) setting transfer counter register (27h to 29h) 03h setting sdram host cpu transfer transfer mode register (20h) 01h setting sdram host cpu transfer release transfer mode register (20h) 00h setting transfer data register (3fh) data read interrupt register 0 (30h) 01h setting transfer data register (3fh) data read transfer data register (3fh) data read sdram host cpu transfer release transfer mode register (20h) 00h setting return y y n interrupt register 0 (30h) 01h n cint? interrupt register 0 (30h): 02h interrupt register 0 (30h): 01h y y n n cint? interrupt register 0 (30h): 01h y y n n cint?
data sheet s15082ej4v0ds 64 pd61051, 61052 5. example for common register usage the pd61051, 61052 operates while the ?command code registe r? is in ?start?. when ?command code register? becomes ?start?, internal cpu reads param eter registers, then starts the operation. additionally, internal register sets ?status register?. register map for system interface register is defined by firmware. with each application, parameter r egisters are changed by the firmware. figure 5-1. host interface register host cpu system interface register instruction ram of internal cpu internal cpu sdram interface sdram dma controller pd61051/61052
data sheet s15082ej4v0ds 65 pd61051, 61052 5.1 register map example address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h comcode 01h ests 02h to 1fh parameters (d efined by each firmware) 20h si ssd sdi msd mi sdw sdr 21h sa19 to sa16 22h sa15 to sa8 23h sa7 to sa0 24h da16 25h da15 to da8 26h da7 to da0 27h tc18 to tc16 28h tc15 to tc8 29h tc7 to tc0 2ah icpu-int 2bh dma- err-m dma- rdy-m dma- done-m 2ch to 2fh interrupt mask (defined by each firmware) 30h dma-err dma-rdy dma- done 31h to 34h interrupt (def ined by each firmware) 35h irom2 to irom0 36h isreq osvld 37h to 3dh 3eh nbr all reset 3fh td7 to td0 : reserved
data sheet s15082ej4v0ds 66 pd61051, 61052 5.2 example of the common regist er which a firmware defines 5.2.1 comcode: command code register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h comcode the host cpu can change the st ate of operation to the co mmand code register. the pd61051/61052 accepts commands to operate in three states as shown in the table below. command code standby / stop 001 start 011 reserved others the command which it is possible to set depend on the internal state. in case of the command whose state transfer is possi ble, the state transfers according to the command. 5.2.2 ests: status register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01h ests this register shows processing state, when command is illegal, the state doesn?t transfer. ests code initial state 000 standby state 001 encoding state 011
data sheet s15082ej4v0ds 67 pd61051, 61052 figure 5-2. command status transition hardware reset initial state (000) standby state (001) 001 : standby 001 : stop 011 : start encoding state (011) valid command in initial state: standby valid command in standby state: start valid command in operation state: stop
data sheet s15082ej4v0ds 68 pd61051, 61052 6. electrical ch aracteristics absolute maximum ratings (t a = 25c) parameter symbol conditions rating unit v dd3 v dd3 , vs gnd 4.6 v supply voltage v dd2 v dd2 , vs gnd pv dd2 , vs pgnd 3.6 v input voltage v in vs gnd3 ? 0.5 to + 4.6 v output voltage v out vs gnd3 ? 0.5 to + 4.6 v output current i out 20 ma permissible loss p d 2 w operating ambient temperature t a 0 to +70 c storage temperature t stg ? 55 to + 125 c caution if any of the parameters exceeds the absolute m aximum ratings, even momentarily, the quality of the product may be impaired. the absolute m aximum ratings are valu es that may physically damage the products. be sure to use the products within the ratings. dc characteristics (t a = 0 to + 70c, v dd3 = 3.3 0.165 v, v dd2 = 2.5 0.2 v) parameter symbol condition min. typ. max. unit v dd3 v dd3 , vs gnd 3.135 3.3 3.465 v supply voltage v dd2 v dd2, vs gnd pv dd2, vs pgnd 2.3 2.5 2.7 v high-level input voltage v ih 2.2 v dd3 + 0.5 v sclk ? 0.5 + 0.6 v low-level input voltage v il except sclk ? 0.5 + 0.7 v high-level output voltage v oh 2.4 v low-level output voltage v ol 0.4 v input leakage current i li except md31 to md0 and cmode1 10 a i dd3 3.3 v power supply 70 ma i pdd 2.5 v pll power supply 15 ma operating current i dd2 internal logic power supply of 2.5 v 510 ma
data sheet s15082ej4v0ds 69 pd61051, 61052 pin capacitance (t a = 25c) parameter symbol conditions min. typ. max. unit input capacitance c i 20 pf output capacitance c o 20 pf i/o capacitance c io 20 pf ac characteristics (t a = 0 to + 70c, v dd3 = 3.3 0.165 v, v dd2 = 2.5 0.2 v, c l = 15 pf, t r = t f = 1 ns) (1) system parameter symbol conditions min. typ. max. unit sclk frequency f sck 27.0 mhz sclk high-level width t sckh duty 40:60 13.2 ns sclk low-level width t sckl duty 40:60 13.2 ns pstop release time1 t stp1 vs v dd3 1 s pstop release time2 t stp2 vs v dd2 1 s pstop release time3 t stp3 vs pv dd2 1 s pstop release time4 t stp4 vs sclk 1 s pstop pulse width t wstp 1 s reset release time t res vs falling edge of pstop 100 s video input reset time t lvres after stable ivclk 600 ns audio reset time t aures after stable amclk 600 ns stc reset time t stres after stable stclk 600 ns reset pulse width t resw after stable all clock 600 ns input rising time t ir vs amclk, stclk, sclk, isclk 3 ns vs ivclk 5 ns input falling time t if vs amclk, stclk, sclk, isclk 3 ns vs ivclk 5 ns output rising time t or 3 ns output falling time t of 3 ns high level, low level clock input v ih t ir , t or t if , t of v il v ih v il t sck = 1/f sck t sckh t sckl
data sheet s15082ej4v0ds 70 pd61051, 61052 reset input v dd3 t stp1 frequency stabilization (10% max. ) t stp3 t stp2 t stp4 t wstp t res v dd2 pv dd2 sclk pstop reset caution notes on power on/off apply power to v dd3 , and v dd2 and pv dd2 at the same time. if it is difficult to apply the power to these pins at the same time, apply the power to v dd2 and pv dd2 first. cut the power of v dd3 , and v dd2 and pv dd2 at the same time. if it is difficult to cut the power of th ese pins at the same time, cut the power of v dd2 and pv dd2 last.
data sheet s15082ej4v0ds 71 pd61051, 61052 ivclk t ivres t stres t aures t stp4 t wstp t res amclk stclk sclk pstop reset
data sheet s15082ej4v0ds 72 pd61051, 61052 ivclk t resw amclk stclk sclk pstop reset ''l'' t ivres t aures t stres
data sheet s15082ej4v0ds 73 pd61051, 61052 (2) video input interface parameter symbol conditions min. typ. max. unit ivclk frequency f ivcks 27 mhz ivclk high-level width t vckh 10 ns ivclk low-level width t vckl 10 ns ivin7 to ivin0 setup time t ivds vs rising edge of ivclk 5 ns ivin7 to ivin0 hold time t ivdh vs rising edge of ivclk 4 ns ivvsync-input setup time t ivvs vs rising edge of ivclk 5 ns ivvsync-input hold time t ivvh vs rising edge of ivclk 4 ns ivhsync-input setup time t ivhs vs rising edge of ivclk 5 ns ivhsync-input hold time t ivhh vs rising edge of ivclk 4 ns ivfld-input setup time t ivfs vs rising edge of ivclk 5 ns ivfld-input hold time t ivfh vs rising edge of ivclk 4 ns yy cb cr cr ivclk ivin7 to ivin0 ivhsync ivvsync ivfld f ivcks t ivckh t ivds t ivvh t ivhh t ivfh t ivvs t ivhs t ivfs t ivdh t ivckl
data sheet s15082ej4v0ds 74 pd61051, 61052 (3) video output interface parameter symbol conditions min. typ. max. unit ovclk frequency f ovcks 27 mhz ovclk high-level width t ovckh 8 ns ovclk low-level width t ovckl 8 ns ovout7 to ovout0 hold time t ovho vs rising edge of ovclk 7 ns ovout7 to ovout0 delay time t ovdo vs rising edge of ovclk 28 ns ovvsync hold time t ovvho vs rising edge of ovclk 7 ns ovvsync delay time t ovvd vs rising edge of ovclk 28 ns ovhsync hold time t ovhho vs rising edge of ovclk 7 ns ovhsync delay time t ovhd vs rising edge of ovclk 28 ns yy cb cr ovclk ovout7 to ovout0 f ovcks t ovckh t ovho t ovdo t ovckl t ovhho t ovvho t ovhd t ovvd ovhsync ovvsync
data sheet s15082ej4v0ds 75 pd61051, 61052 (4) audio input interface parameter symbol conditions min. typ. max. unit bit data-in setup time t acds vs iabck 37 ns bit data-in hold time t acdh vs iabck 37 ns lrck-in setup time t acls vs iabck 100 ns lrck-in hold time t aclh vs iabck 37 ns iabck iabd ialrck t acds t acdh t aclh t acls
data sheet s15082ej4v0ds 76 pd61051, 61052 (5) audio output interface parameter symbol conditions min. typ. max. unit bit data-out hold time t acdho vs oabck ? 5 ns bit data-out delay time t acdd vs oabck 25 ns lrck-out hold time t aclho vs oabck ? 5 ns lrck-out delay t acld vs oabck 25 ns bck-out duty ratio d bck 50 % amclk duty ratio d amclk 50 % amclk frequency f amclk 18.432 mhz oabck oabd oalrck t acdho t acdd t aclho t acld
data sheet s15082ej4v0ds 77 pd61051, 61052 (6) stream input interface (a) parallel stream input valid mode parameter symbol conditions min. typ. max. unit isclk cycle t isccyc 80 ns isclk low-level width t isclw 37 ns isclk high-level width t ischw 37 ns isreq output hold time t isrqho vs active edge of isclk 0 ns isvld setup time t isvs vs active edge of isclk 7 ns isvld hold time t isvh vs active edge of isclk 3 ns issync setup time t isss vs active edge of isclk 7 ns issync hold time t issh vs active edge of isclk 3 ns is7 to is0 setup time t isds vs active edge of isclk 7 ns is7 to is0 hold time t isdh vs active edge of isclk 3 ns data cycle time t dcyc 80 ns remark isreq is effective only when it works by the mast er mode. isreq becomes invalid asynchronously to isclk. isreq output delay time doesn't prescribe to isclk. isvld (i) is7 to is0 (i) issync (i) isclk (i) isreq (o) valid data valid data valid data valid data no received data t isclw t isvs t isvh t dcyc t isdh t issh t isds t isss t ischw t iscyc t isrqho valid data valid data valid data valid data 1st of packet remark issync is active high, sreq is active high and isclk is active high edge.
data sheet s15082ej4v0ds 78 pd61051, 61052 strobe mode parameter symbol conditions min. typ. max. unit isstb low-level width t isstlw 37 ns isstb high-level width t issthw 37 ns isreq output hold time t isrqho vs active edge of isstb 0 ns issync setup time t isss vs active edge of isstb 7 ns issync hold time t issh vs active edge of isstb 3 ns is7 to is0 setup time t isds vs active edge of isstb 7 ns is7 to is0 hold time t isdh vs active edge of isstb 3 ns data cycle time t dcyc 80 ns remark isreq becomes invalid asynchronously to isstb. isreq output delay time does n't prescribe to isstb. isstb (i) is7 to is0 (i) issync (i) isreq (o) valid data valid data valid data valid data valid data valid data valid data valid data 1st of packet no received data t issthw t isstlw t dcyc t isdh t issh t isds t isss t isrqho remark issync is active high, isreq is active low and isstb is active high edge.
data sheet s15082ej4v0ds 79 pd61051, 61052 (b) serial stream input parameter symbol conditions min. typ. max. unit isclk period t isscw 15.6 ns isclk low-level width t issclw 5.0 ns isclk high-level width t isschw 5.0 ns isvld setup time t issvs vs active edge of isclk 2.5 ns isvld hold time t issvh vs active edge of isclk 2.5 ns issync setup time t issss vs active edge of isclk 2.5 ns issync hold time t isssh vs active edge of isclk 2.5 ns iserr setup time t isses vs active edge of isclk 2.5 ns iserr hold time t isseh vs active edge of isclk 2.5 ns is0 setup time t issds vs active edge of isclk 2.5 ns is0 hold time t issdh vs active edge of isclk 2.5 ns remark setup and hold time provide to the activist edge of isclk. isclk iserr t isscw t issclw t isschw t isses t isseh issync t issss t isssh isvld t issvs t issvh is0 t issds t issdh remark isclk is active high edge.
data sheet s15082ej4v0ds 80 pd61051, 61052 (7) stream output interface (a) parallel stream data output valid and master mode parameter symbol conditions min. typ. max. unit active rising edge 30 ns osclk low-level width t osclw active falling edge 70 ns active rising edge 70 ns osclk high-level width t oschw active falling edge 30 ns osvld hold time t osvho vs active edge of osclk 30 ns osvld delay time t osvd vs non active edge of osclk ? 5 + 5 ns ossync hold time t ossho vs active edge of osclk 30 ns ossync delay time t ossd vs non active edge of osclk ? 5 + 5 ns os7 to os0 hold time t osdho vs active edge of osclk 30 ns os7 to os0 delay time t osdd vs non active edge of osclk ? 5 + 5 ns data cycle time t dcyc2 105 ns remark osvld is active high, ossync is active high and osclk is active high edge. osclk osvld os7 to os0 valid data valid data valid data valid data valid data valid data valid data invalid data invalid data ossync t ossd t ossho 188 bytes 1st of packet t osvho t dcyc2 t osvd t osdd t osdho t oschw t osclw
data sheet s15082ej4v0ds 81 pd61051, 61052 strobe and byte mode parameter symbol conditions min. typ. max. unit osreq high-level time t osrhw 2 stclk active rising edge 100 ns osstb high-level width t ossthw active falling edge 70 ns active rising edge 70 ns osstb low-level width t osstlw active falling edge 100 ns osreq hold time t osrrd vs active edge of osrdy 0 ns t ostrq1 vs active edge of osstb 0 ns osreq hold time t ostrq2 vs non active edge of osstb 0 ns t osrstd1 vs active edge of osreq 2 3 stclk osstb delay time t osrstd2 vs non active edge of osreq 3 stclk osrdy delay time t osstrd1 vs non active edge of osstb 3 stclk ossync-out delay time t ossd vs non active edge of osstb ? 5 + 5 ns ossync-out hold time t ossho vs active edge of osstb 70 ns os7 to os0 out delay time t osdd vs non active edge of osstb ? 5 + 5 ns os7 to os0 out hold time t osdho vs active edge of osstb 70 ns ossync os7-os0 osstb osreq osrdy t ossd t osdd t osstrd1 t osrstd1 t osrstd2 t ossho t osdho t ostrq1 t osrhw t osrrd t osstlw t ossthw t ostrq2 remark ossync is active high, osrdy is active low and osstb is active high edge.
data sheet s15082ej4v0ds 82 pd61051, 61052 (b) serial stream data output parameter symbol conditions min. typ. max. unit osclk period t osscw 37 ns osclk low-level width t ossclw 10 ns osclk high-level width t osschw 10 ns os0 delay time t ossdd vs active edge of osclk 27 ns os0 hold time t ossdho vs active edge of osclk 5.0 ns osvld delay time t ossvd vs active edge of osclk 27 ns osvld hold time t ossvho vs active edge of osclk 5.0 ns ossync delay time t osssd vs active edge of osclk 27 ns ossync hold time t osssho vs active edge of osclk 5.0 ns remarks 1. active edge of osclk is able to change according to the following circuit. 2. period of the osclk is provided by stclk. osclk t osscw t ossclw t osschw ossync t osssho t osssd osvld t ossho t ossvd os0 t ossdho t ossd remark osclk is active high edge.
data sheet s15082ej4v0ds 83 pd61051, 61052 (8) sdram interface parameter symbol conditions min. typ. max. unit mclk cycle time t ck 12.3 ns mclk high-level width t ch 3.5 ns mclk low-level width t cl 3.5 ns md31 to md0-out hold time t oh vs mclk 1.5 ns md31 to md0-out delay time t od vs mclk 9 ns md31 to md0 low-z output time t lz vs mclk 0 ns md31 to md0 high-z output time t hz vs mclk 9 ns md31 to md0-in setup time t ds vs mclk 6 ns md31 to md0-in hold time t dh vs mclk 2 ns ma13 to ma0 delay time t ad vs mclk 9 ns ma13 to ma0 hold time t ah vs mclk 1.5 ns mclke delay time t cks vs mclk 9 ns mclke hold time t ckh vs mclk 1.5 ns command delay time t cmd vs mclk 9 ns command hold time t cmh vs mclk 1.5 ns act ref/act command period t rc 12 mclk ref ref/act command period t rc1 12 mclk act pre command period t ras 12 mclk pre act command period t rp 12 mclk act r/w command delay time t rcd 3 mclk act (0) act (1) command period t rrd 4 mclk data-in to pre command period t dpl 2 mclk data-in to act (ref) command period (auto pre-charge) t dal 6 mclk mode register set cycle period t rsc 2 mclk refresh time (4096 refresh cycle) t ref 50 ms remark ref: refresh, act: active, pre: pre-charge
data sheet s15082ej4v0ds 84 pd61051, 61052 read timing (manual pre-charge, bur st length = 4, cas latency = 3) t0 mclk mclke mcs mras mcas mwe ma13 ma12 ma10 ma9 to ma0 mdqm md31 to md0 active command for bank a active command for bank a read command for bank a precharge command for bank a low hi-z hi-z t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t rcd t ah t ck t ras t rc t ds t dh t rp t ad t ckh t ck t cl t ch t cmd t cmh
data sheet s15082ej4v0ds 85 pd61051, 61052 read timing (auto pre-charge, burst length = 4, cas latency = 3) t0 mclk mclke mcs mras mcas mwe ma13 ma12 ma10 ma9 to ma0 mdqm md31 to md0 active command for bank a active command for bank b active command for bank a read with auto precharge command for bank a low hi-z hi-z t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t rcd t ah t ck t rrd t ras t rc t ds t dh t ad t ckh t ck t cl t ch t cmd t cmh
data sheet s15082ej4v0ds 86 pd61051, 61052 write timing (burst length = 4, cas latency = 3) t0 mclk mclke mcs mras mcas mwe ma13 ma12 ma10 ma9 to ma0 mdqm md31 to md0 active command for bank a active command of bank b active command for bank b low hi-z hi-z t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 precharge command for bank b t rcd t dal t rp t dpl t ah t rc t rrd t rcd t ras t rc t oh t hz t lz t od t ad t ckh t ck t ch t ckd t cl t cmd t cmh t14 t15 t16 t17 t18 t19 t20 t21 daa1 daa2 daa3 daa4 dba1 dba2 dba3 dba4 write with auto precharge command for bank a write with auto precharge command for bank b active command for bank a
data sheet s15082ej4v0ds 87 pd61051, 61052 (9) host cpu interface (a) parallel bus interf ace: wait mode (1/2) parameter symbol conditions min. typ. max. unit ccs ca5 to ca0 delay time t cad vs falling edge of ccs do not care - - - ns ccs cwait delay time t cwad1 vs falling edge of ccs ccs later than cre/cwe 15 ns ccs cwait release time t crdy vs falling edge of ccs ccs later than cre/cwe 175 ns ca5 to ca0 cre delay time t ard vs ca5 to ca0 ? 20 ns ccs cre delay time t crd vs falling edge of ccs ? 20 ns cre cwait delay time t rwd1 vs falling edge of cre 15 ns cre cwait release time t rrd vs falling edge of cre 175 ns ccs cd7 to cd0 low-z time t cdld vs falling edge of ccs data not fixed 0 ns cre cd7 to cd0 low-z time t rdld vs falling edge of cre data not fixed 0 ns ccs cd7 to cd0 delay time t cdd vs falling edge of ccs data fixed 150 ns cre cd7 to cd0 delay time t rdd vs falling edge of cre data fixed 150 ns cre cd7 to cd0 hold time t rdh vs rising edge of cre earlier than rising edge of ccs 0 ns cre ca5 to ca0 hold time t rah vs rising edge of cre ? 27 ns cre ccs hold time t rch vs rising edge of cre ? 27 ns ccs cd7 to cd0 hold time t cdrh vs rising edge of ccs earlier than rising edge of cre 0 ns cd7 to cd0 cwait release time t cdw vs cd7 to cd0 fixed 10 ns cd7 to cd0 hi-z delay time t cdzd vs rising edge of cre or ccs 12 ns ca5 to ca0 cwe delay time t awd vs ca5 to ca0 ? 28 ns ccs cwe delay time t cwd vs falling edge of ccs ? 20 ns cwe cwait delay time t wwd1 vs falling edge of cwe 15 ns cwe cwait release time t wrd vs falling edge of cwe 150 ns cwe cd7 to cd0 delay time t wdd vs falling edge of cwe until data fixed 30 ns cwe cd7 to cd0 hold time t wdh vs rising edge of cwe ? 7 ns
data sheet s15082ej4v0ds 88 pd61051, 61052 (2/2) parameter symbol conditions min. typ. max. unit cwe ca5 to ca0 hold time t wah vs rising edge of cwe ? 27 ns cwe ccs hold time t wch vs rising edge of cwe ? 27 ns ccs cd7 to cd0 hold time t cdwh vs rising edge of ccs 0 ns ccs cwait release time t cwad2 vs rising edge of ccs 0 15 ns cwait release cwe/cre hold time t cwr vs cwait release 0 ns cwait release cd5 to cd0 hold time t cwa vs cwait release 0 ns cwait release css hold time t cwc vs cwait release 0 ns cre/cwe recovery time t cac 25 ns access cycle after other device t ccyc 200 ns remark if ccs change to "h" in wait cycle, it cancels cwai t. in access time, don't make ccs "h" until wait released.
data sheet s15082ej4v0ds 89 pd61051, 61052 wait mode (wait active low, read cycle) ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t ard t cad t cdld t cdd t cac t cwad1 t crdy t cdrh t rch t rah t rwd1 t rrd t crd t cdzd t rdld t rdd t cdzd t rdh t cwr t cdw t cwc t cwa t cac wait mode (wait active low, write cycle) ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t awd t cad t cac t cwad1 t crdy t cdwh t wch t wah t wwd1 t wrd t cwd t wdd t wdh t cwr t cwc t cwa t wdd t cac
data sheet s15082ej4v0ds 90 pd61051, 61052 wait mode (wait active high, read cycle) ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t ard t cad t cdld t cdd t cac t cwad1 t crdy t cdrh t rch t rah t rwd1 t rrd t crd t cdzd t rdld t rdd t cdzd t rdh t cwr t cdw t cwc t cwa t cac wait mode (wait active high, write cycle) ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t awd t cad t cac t cwad1 t crdy t cdwh t wch t wah t wwd1 t wrd t cwd t wdd t wdh t cwr t cwc t cwa t wdd t cac
data sheet s15082ej4v0ds 91 pd61051, 61052 ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t ccyc t ccyc t ccyc ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t ccyc t ccyc t ccyc
data sheet s15082ej4v0ds 92 pd61051, 61052 (b) parallel bus interface: ready mode (1/2) parameter symbol conditions min. typ. max. unit ccs ca5 to ca0 delay time t cad vs falling edge of ccs do not care - - - ns ccs cwait delay time t cwad1 vs falling edge of ccs ccs later than cre/cwe 15 ccs cwait ready time t crdy vs falling edge of ccs ccs later than cre/cwe 175 ns ca5 to ca0 cre delay time t ard vs ca5 to ca0 ? 20 ns ccs cre delay time t crd vs falling edge of ccs ? 20 ns cre cwait ready time t rrd vs falling edge of cre 175 ns ccs cd7 to cd0 low-z time t cdld vs falling edge of ccs data not fixed 0 ns cre cd7 to cd0 low-z time t rdld vs falling edge of cre data not fixed 0 ns ccs cd7 to cd0 delay time t cdd vs falling edge of ccs data fixed 150 ns cre cd7 to cd0 delay time t rdd vs falling edge of cre data fixed 150 ns cre cd7 to cd0 hold time t rdh vs rising edge of cre earlier than rising edge of ccs 0 ns cre ca5 to ca0 hold time t rah vs rising edge of cre ? 27 ns cre ccs hold time t rch vs rising edge of cre ? 27 ns ccs cd7 to cd0 hold time t cdrh vs rising edge of ccs earlier than rising edge of cre 0 ns cd7 to cd0 cwait ready time t cdw vs cd7 to cd0 fixed 10 ns cd7 to cd0 high-z delay time t cdzd vs rising edge of cre or ccs 12 ns ca5 to ca0 cwe delay time t awd vs ca5 to ca0 ? 28 ns ccs cwe delay time t cwd vs falling edge of ccs ? 20 ns cwe cwait ready time t wrd vs falling edge of cwe 150 ns cwe cd7 to cd0 delay time t wdd vs falling edge of cwe until data fixed 30 ns cwe cd7 to cd0 hold time t wdh vs rising edge of cwe ? 7 ns cwe ca5 to ca0 hold time t wah vs rising edge of cwe ? 27 ns cwe ccs hold time t wch vs rising edge of cwe ? 27 ns ccs cd7 to cd0 hold time t cdwh vs rising edge of ccs 0 ns cre cwait release time t rwd2 vs rising edge of cre 0 15 ns
data sheet s15082ej4v0ds 93 pd61051, 61052 (2/2) parameter symbol conditions min. typ. max. unit cwe cwait release time t wwd2 vs rising edge of cwe 0 15 ns ccs cwait release time t cwad2 vs rising edge of ccs 0 15 ns cwait ready cwe/cre hold time t cwr vs cwait ready 0 ns cwait ready ca5 to ca0 hold time t cwa vs cwait ready 0 ns cwait ready ccs hold time t cwc vs cwait ready 0 ns cre/cwe recovery time t cac 25 ns access cycle after other device t ccyc 200 ns remark if ccs change to "h" in wait cycle, it cancels cwai t. in access time, don't make ccs "h" until wait becomes ready.
data sheet s15082ej4v0ds 94 pd61051, 61052 ready mode (ready active high, read cycle) ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t ard t cad t cdld t cdd t cac t cwad2 t crdy t cdrh t rch t rah t rwd2 t rrd t crd t cdzd t rdld t rdd t cdzd t rdh t cwr t cdw t cwc t cwa t cac ready mode (ready active high, write cycle) ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t awd t cad t cac t crdy t cdwh t wch t wah t wrd t cwd t wdd t wdh t cwr t cwc t cwa t wdd t cac t cwad2 t wwd2
data sheet s15082ej4v0ds 95 pd61051, 61052 ready mode (ready active low, read cycle) ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t ard t cad t cdld t cdd t cac t cwad2 t crdy t cdrh t rch t rah t rwd2 t rrd t crd t cdzd t rdld t rdd t cdzd t rdh t cwr t cdw t cwc t cwa t cac ready mode (ready active low, write cycle) ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t awd t cad t cac t crdy t cdwh t wch t wah t wrd t cwd t wdd t wdh t cwr t cwc t cwa t wdd t cac t cwad2 t wwd2
data sheet s15082ej4v0ds 96 pd61051, 61052 ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t ccyc t ccyc t ccyc ccs ca5 to ca0 cre cd7 to cd0 cwait cwe t ccyc t ccyc t ccyc
data sheet s15082ej4v0ds 97 pd61051, 61052 (c) parallel bus interface: fixed wait mode parameter symbol conditions min. typ. max. unit ccs ca5 to ca0 delay time t cad vs falling edge of ccs do not care - - - ns cre pulse width t rw 175 ns ca5 to ca0 cre delay time t ard vs ca5 to ca0 ? 20 ns ccs cre delay time t crd vs falling edge of ccs ? 20 ns ccs cd7 to cd0 low-z time t cdld vs falling edge of ccs data not fixed 0 ns cre cd7 to cd0 low-z time t rdld vs falling edge of cre data not fixed 0 ns ccs cd7 to cd0 delay time t cdd vs falling edge of ccs data fixed 150 ns cre cd7 to cd0 delay time t rdd vs falling edge of cre data fixed 150 ns cre cd7 to cd0 hold time t rdh vs rising edge of cre earlier than rising edge of ccs 0 ns cre ca5 to ca0 hold time t frah vs rising edge of cre ? 27 ns cre ccs hold time t frch vs rising edge of cre ? 27 ns ccs cd7 to cd0 hold time t cdrh vs rising edge of ccs 0 ns cd7 to cd0 high-z delay time t cdzd vs rising edge of cre or ccs 12 ns cwe pulse width t ww 150 ns ca5 to ca0 cwe delay time t awd vs ca5 to ca0 ? 28 ns ccs cwe delay time t cwd vs falling edge of ccs ? 20 ns cwe cd7 to cd0 delay time t wdd vs falling edge of cwe until data fixed 30 ns cwe cd7 to cd0 hold time t wdh vs rising edge of cwe ? 7 ns cwe ca5 to ca0 hold time t fwah vs rising edge of cwe ? 27 ns cwe ccs hold time t fwch vs rising edge of cwe ? 27 ns ccs cd7 to cd0 hold time t cdwh vs rising edge of ccs 0 ns cre/cwe recovery time t cac 25 ns access cycle after other device t ccyc 200 ns
data sheet s15082ej4v0ds 98 pd61051, 61052 fixed wait mode (read cycle) ccs ca5 to ca0 cre cd7 to cd0 cwe t ard t cad t cdld t cdd t cac t cdrh t frch t frah t crd t cdzd t rdld t rdd t cdzd t rdh t rw t cac fixed wait mode (write cycle) ccs ca5 to ca0 cre cd7 to cd0 cwe t awd t cad t cac t cdwh t fwch t fwah t ww t cwd t wdd t wdh t wdd t cac
data sheet s15082ej4v0ds 99 pd61051, 61052 ccs ca5 to ca0 cre cd7 to cd0 cwe t ccyc t ccyc t ccyc ccs ca5 to ca0 cre cd7 to cd0 cwe t ccyc t ccyc t ccyc
data sheet s15082ej4v0ds 100 pd61051, 61052 (10) serial bus interface (a) serial bus interface parameter symbol conditions min. typ. max. unit ccs csclk delay time t csck vs falling edge of ccs 10 ns ccs csdi delay time t csdi vs falling edge of ccs 10 ns csdi setup time t csds vs rising edge of csclk 10 ns csdi hold time t csdh vs rising edge of csclk 10 ns csdo hold time t csdho vs falling edge of csclk 0 ns csdo delay time t csdd vs falling edge of csclk 15 ns csclk ccs hold time t ccks vs rising edge of csclk 75 ns ccs high-level width t cshw 125 ns csclk cycle time t ckcyc 100 ns csclk high-level width t cschw 40 ns csclk high-level width t csclw 40 ns ccs csclk csdi csdo t csck t csdi t csds t csdh t csdho t csdd t ckcs t cschw t csclw
data sheet s15082ej4v0ds 101 pd61051, 61052 a5 a4 a3 a1 a0 w x d5 d3 d2 d1 d0 d7 d6 xx x a5 a4 a3 a1 a0 r x x x xxxxx x xx x xx d4 d3 d2 d1 d0 d7 [data write] [data read] ccs csclk csdi csdo ccs csclk csdi csdo xx t csck t ckcyc t csdi t csds t csdh t csds t csdh t csds t csdh t ckcs t cshw t csck t ckcyc t csdi t csdho t csdd t ckcs t cshw a2 d4 a2 d5 d6 (b) instruction rom interface parameter symbol conditions min. typ. max. unit address setup time t fars vs falling edge of foe 0 ns address hold time t farh vs rising edge of foe 5 ns foe low-level width t frlw 70 225 ns foe high-level width t frhw 24 ns data setup time t fds vs rising edge of foe 25 ns data hold time t fdh vs rising edge of foe 0 ns data high-z output time t fdhl vs rising edge of foe 60 ns fa19 to fa0 foe fd7 to fd0 t fars hi-z hi-z hi-z t farh t frhw t frlw t fds t fdh t fdhl
data sheet s15082ej4v0ds 102 pd61051, 61052 7. package drawing 208-pin plastic qfp (fine pitch) (28x28) item millimeters f g 1.25 1.25 b c 28.0 0.2 28.0 0.2 h 0.22 i 0.10 s 3.8 max. k 1.3 0.2 l 0.5 0.2 m 0.17 n 0.10 p 3.2 0.1 + 0.05 ? 0.04 j 0.5 (t.p.) p208gd-50-lml,mml,sml,wml-7 + 0.03 ? 0.07 r5 5 j i ns s detail of lead end q 0.4 0.1 m note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 1 208 52 53 156 157 105 104 c a b q r h k m l d p g f s a 30.6 0.2 d 30.6 0.2
data sheet s15082ej4v0ds 103 pd61051, 61052 8. recommended soldering conditions the pd61051, 61052 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 8-1. surface-mounted soldering conditions pd61051gd-lml: 208-pin plastic qfp (fine pitch) (28 28) pd61051gd-lml-a note1 : 208-pin plastic qfp (fine pitch) (28 28) pd61052gd-lml: 208-pin plastic qfp (fine pitch) (28 28) pd61052gd-lml-a note1 : 208-pin plastic qfp (fine pitch) (28 28) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c ir35-207-3 time: 30 sec. max. (at 210c or higher) count: three times or fewer exposure limit: 7 days note2 (after that, prebake at 125c for 20 to 72 hours) vps package peak temperature: 215c vp15-207-3 time: 40 sec. max. (at 200c or higher) count: three times or fewer exposure limit: 7 days note2 (after that, prebake at 125c for 20 to 72 hours) partial heating pin temperature: 300c max. ? time: 3 sec. max. (per pin row) notes 1. lead-free product 2. after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period. caution do not use two or more so ldering methods in combination ( except for partial heating method).
data sheet s15082ej4v0ds 104 pd61051, 61052 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
data sheet s15082ej4v0ds 105 pd61051, 61052 [memo]
pd61051, 61052 dolby is a trademark of dolby laboratories. the information in this document is current as of november, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

▲Up To Search▲

Price & Availability of UPD61051GD-LML

	To Download UPD61051GD-LML Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .